Brian Keith Dutton

Array ( [id] => 4031450 [patent_doc_number] => 05963838 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Method of manufacturing a semiconductor device having wiring layers within the substrate' [patent_app_type] => 1 [patent_app_number] => 8/521105 [patent_app_country] => US [patent_app_date] => 1995-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 78 [patent_figures_cnt] => 137 [patent_no_of_words] => 20156 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963838.pdf [firstpage_image] =>[orig_patent_app_number] => 521105 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3825889 [patent_doc_number] => 05759870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Method of making a surface micro-machined silicon pressure sensor' [patent_app_type] => 1 [patent_app_number] => 8/520055 [patent_app_country] => US [patent_app_date] => 1995-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 27 [patent_no_of_words] => 2923 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/759/05759870.pdf [firstpage_image] =>[orig_patent_app_number] => 520055 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3665402 [patent_doc_number] => 05599724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'FET having part of active region formed in semiconductor layer in through hole formed in gate electrode and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/518855 [patent_app_country] => US [patent_app_date] => 1995-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 5312 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/599/05599724.pdf [firstpage_image] =>[orig_patent_app_number] => 518855 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3860665 [patent_doc_number] => 05795797 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Method of making memory chips using memory tester providing fast repair' [patent_app_type] => 1 [patent_app_number] => 8/516709 [patent_app_country] => US [patent_app_date] => 1995-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 7576 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/795/05795797.pdf [firstpage_image] =>[orig_patent_app_number] => 516709 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3664447 [patent_doc_number] => 05597746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Method of forming field effect transistors relative to a semiconductor substrate and field effect transistors produced according to the method' [patent_app_type] => 1 [patent_app_number] => 8/512804 [patent_app_country] => US [patent_app_date] => 1995-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2505 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/597/05597746.pdf [firstpage_image] =>[orig_patent_app_number] => 512804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3734420 [patent_doc_number] => 05698454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Method of making a reverse blocking IGBT' [patent_app_type] => 1 [patent_app_number] => 8/508753 [patent_app_country] => US [patent_app_date] => 1995-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3850 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/698/05698454.pdf [firstpage_image] =>[orig_patent_app_number] => 508753 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3607966 [patent_doc_number] => 05589411 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Process for fabricating a high-voltage MOSFET' [patent_app_type] => 1 [patent_app_number] => 8/508515 [patent_app_country] => US [patent_app_date] => 1995-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2138 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/589/05589411.pdf [firstpage_image] =>[orig_patent_app_number] => 508515 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3815009 [patent_doc_number] => 05770471 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Method of making semiconductor laser with aluminum-free etch stopping layer' [patent_app_type] => 1 [patent_app_number] => 8/508211 [patent_app_country] => US [patent_app_date] => 1995-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 6362 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/770/05770471.pdf [firstpage_image] =>[orig_patent_app_number] => 508211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3694015 [patent_doc_number] => 05650347 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Method of manufacturing a lightly doped drain MOS transistor' [patent_app_type] => 1 [patent_app_number] => 8/507557 [patent_app_country] => US [patent_app_date] => 1995-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 1729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/650/05650347.pdf [firstpage_image] =>[orig_patent_app_number] => 507557 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3705194 [patent_doc_number] => 05654218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Method of manufacturing inverse t-shaped transistor' [patent_app_type] => 1 [patent_app_number] => 8/507049 [patent_app_country] => US [patent_app_date] => 1995-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 2991 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654218.pdf [firstpage_image] =>[orig_patent_app_number] => 507049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3681737 [patent_doc_number] => 05633183 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'FET having minimized parasitic gate capacitance' [patent_app_type] => 1 [patent_app_number] => 8/500649 [patent_app_country] => US [patent_app_date] => 1995-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1687 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/633/05633183.pdf [firstpage_image] =>[orig_patent_app_number] => 500649 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3657724 [patent_doc_number] => 05591651 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Method of making a bipolar stripe transistor structure' [patent_app_type] => 1 [patent_app_number] => 8/501757 [patent_app_country] => US [patent_app_date] => 1995-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 2556 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/591/05591651.pdf [firstpage_image] =>[orig_patent_app_number] => 501757 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3785895 [patent_doc_number] => 05736435 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Process for fabricating a fully self-aligned soi mosfet' [patent_app_type] => 1 [patent_app_number] => 8/497317 [patent_app_country] => US [patent_app_date] => 1995-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3475 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/736/05736435.pdf [firstpage_image] =>[orig_patent_app_number] => 497317 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3660406 [patent_doc_number] => 05656530 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Method of making electric field emitter device for electrostatic discharge protection of integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/494514 [patent_app_country] => US [patent_app_date] => 1995-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3289 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/656/05656530.pdf [firstpage_image] =>[orig_patent_app_number] => 494514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3597876 [patent_doc_number] => 05559046 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Semiconductor device having a hollow around a gate electrode and a method for producing the same' [patent_app_type] => 1 [patent_app_number] => 8/494371 [patent_app_country] => US [patent_app_date] => 1995-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 5062 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559046.pdf [firstpage_image] =>[orig_patent_app_number] => 494371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3686836 [patent_doc_number] => 05643807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Method of manufacturing a semiconductor device comprising a buried channel field effect transistor' [patent_app_type] => 1 [patent_app_number] => 8/491753 [patent_app_country] => US [patent_app_date] => 1995-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 5437 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/643/05643807.pdf [firstpage_image] =>[orig_patent_app_number] => 491753 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3744939 [patent_doc_number] => 05716862 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'High performance PMOSFET using split-polysilicon CMOS process incorporating advanced stacked capacitior cells for fabricating multi-megabit DRAMS' [patent_app_type] => 1 [patent_app_number] => 8/491179 [patent_app_country] => US [patent_app_date] => 1995-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 3052 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/716/05716862.pdf [firstpage_image] =>[orig_patent_app_number] => 491179 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3529614 [patent_doc_number] => 05583071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Image sensor with improved output region for superior charge transfer characteristics' [patent_app_type] => 1 [patent_app_number] => 8/489599 [patent_app_country] => US [patent_app_date] => 1995-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 3537 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/583/05583071.pdf [firstpage_image] =>[orig_patent_app_number] => 489599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3760417 [patent_doc_number] => 05741730 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'Flexible IC layout method' [patent_app_type] => 1 [patent_app_number] => 8/489595 [patent_app_country] => US [patent_app_date] => 1995-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2097 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/741/05741730.pdf [firstpage_image] =>[orig_patent_app_number] => 489595 [rel_patent_id] =>[rel_patent_doc_number] =>)