Search

Brian M. Epstein

Examiner (ID: 394, Phone: (571)270-5389 , Office: P/3628 )

Most Active Art Unit
3628
Art Unit(s)
3683, 3628, 3625
Total Applications
298
Issued Applications
97
Pending Applications
2
Abandoned Applications
197

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14785053 [patent_doc_number] => 20190267424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => Method for Manufacturing Optical Sensor Arrangements And Housing For An Optical Sensor [patent_app_type] => utility [patent_app_number] => 16/346273 [patent_app_country] => US [patent_app_date] => 2017-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16346273 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/346273
Method for manufacturing optical sensor arrangements and housing for an optical sensor Oct 18, 2017 Issued
Array ( [id] => 12181607 [patent_doc_number] => 20180040543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'LEAD FRAME AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 15/785980 [patent_app_country] => US [patent_app_date] => 2017-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3492 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15785980 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/785980
LEAD FRAME AND METHOD FOR MANUFACTURING SAME Oct 16, 2017 Abandoned
Array ( [id] => 15532471 [patent_doc_number] => 20200058541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => METHOD OF TRANSFERRING DEVICE LAYER TO TRANSFER SUBSTRATE AND HIGHLY THERMAL CONDUCTIVE SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/346176 [patent_app_country] => US [patent_app_date] => 2017-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8272 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16346176 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/346176
Method of transferring device layer to transfer substrate and highly thermal conductive substrate Oct 12, 2017 Issued
Array ( [id] => 15547811 [patent_doc_number] => 10573697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Organic EL display device [patent_app_type] => utility [patent_app_number] => 15/730113 [patent_app_country] => US [patent_app_date] => 2017-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 5506 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15730113 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/730113
Organic EL display device Oct 10, 2017 Issued
Array ( [id] => 12188691 [patent_doc_number] => 20180047626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'THRU-SILICON-VIA STRUCTURES' [patent_app_type] => utility [patent_app_number] => 15/724493 [patent_app_country] => US [patent_app_date] => 2017-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2536 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15724493 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/724493
Thru-silicon-via structures Oct 3, 2017 Issued
Array ( [id] => 13785529 [patent_doc_number] => 20190006303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => SEMICONDUCTOR DEVICE AND BUMP FORMATION PROCESS [patent_app_type] => utility [patent_app_number] => 15/715659 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715659 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715659
Semiconductor device and bump formation process Sep 25, 2017 Issued
Array ( [id] => 13819623 [patent_doc_number] => 10186586 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-22 [patent_title] => Semiconductor device and method for forming the semiconductor device [patent_app_type] => utility [patent_app_number] => 15/715236 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4273 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715236 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715236
Semiconductor device and method for forming the semiconductor device Sep 25, 2017 Issued
Array ( [id] => 13271199 [patent_doc_number] => 10147686 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-04 [patent_title] => Transistor with shield structure, packaged device, and method of manufacture [patent_app_type] => utility [patent_app_number] => 15/715623 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6291 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715623 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715623
Transistor with shield structure, packaged device, and method of manufacture Sep 25, 2017 Issued
Array ( [id] => 14110381 [patent_doc_number] => 20190096866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/715169 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5281 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715169 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715169
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Sep 25, 2017 Abandoned
Array ( [id] => 12595608 [patent_doc_number] => 20180090366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => INTEGRATED CIRCUIT HAVING A PLURALITY OF ACTIVE LAYERS AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/715619 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5256 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715619 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715619
Integrated circuit having a plurality of active layers and method of fabricating the same Sep 25, 2017 Issued
Array ( [id] => 14110251 [patent_doc_number] => 20190096801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => SEMICONDUCTOR DEVICE WITH INTERCONNECTING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/715327 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9844 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715327 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715327
Semiconductor device with interconnecting structure and method for manufacturing the same Sep 25, 2017 Issued
Array ( [id] => 14301031 [patent_doc_number] => 10290647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Three-dimensional memory device containing structurally reinforced pedestal channel portions and method of making the same [patent_app_type] => utility [patent_app_number] => 15/715629 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 31 [patent_no_of_words] => 15617 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715629 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715629
Three-dimensional memory device containing structurally reinforced pedestal channel portions and method of making the same Sep 25, 2017 Issued
Array ( [id] => 13099113 [patent_doc_number] => 10068902 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-04 [patent_title] => Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method [patent_app_type] => utility [patent_app_number] => 15/715220 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 57 [patent_no_of_words] => 15562 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715220 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715220
Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method Sep 25, 2017 Issued
Array ( [id] => 13559079 [patent_doc_number] => 20180331087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => STACKED SEMICONDUCTOR PACKAGE HAVING MOLD VIAS AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/715449 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715449 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715449
Stacked semiconductor package having mold vias and method for manufacturing the same Sep 25, 2017 Issued
Array ( [id] => 16249524 [patent_doc_number] => 10748899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Epitaxial source and drain structures for high voltage devices [patent_app_type] => utility [patent_app_number] => 15/715541 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6056 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715541 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715541
Epitaxial source and drain structures for high voltage devices Sep 25, 2017 Issued
Array ( [id] => 13349653 [patent_doc_number] => 20180226366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/715237 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715237 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715237
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Sep 25, 2017 Abandoned
Array ( [id] => 13909181 [patent_doc_number] => 20190043795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => METHOD FOR FORMING A HOMOGENEOUS BOTTOM ELECTRODE VIA (BEVA) TOP SURFACE FOR MEMORY [patent_app_type] => utility [patent_app_number] => 15/715487 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715487 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715487
Method for forming a homogeneous bottom electrode via (BEVA) top surface for memory Sep 25, 2017 Issued
Array ( [id] => 12650961 [patent_doc_number] => 20180108818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => LIGHT-EMITTING MODULE AND LIGHTING FIXTURE [patent_app_type] => utility [patent_app_number] => 15/715592 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715592 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715592
LIGHT-EMITTING MODULE AND LIGHTING FIXTURE Sep 25, 2017 Abandoned
Array ( [id] => 12778933 [patent_doc_number] => 20180151479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 15/715544 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715544 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715544
Semiconductor device and manufacturing method of the same Sep 25, 2017 Issued
Array ( [id] => 14110329 [patent_doc_number] => 20190096840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/715132 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715132 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715132
Integrated fan-out package and manufacturing method thereof Sep 24, 2017 Issued
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