Search

Brian N. Vinson

Examiner (ID: 9385)

Most Active Art Unit
2911
Art Unit(s)
2901, 2911, 2900, 2913
Total Applications
12036
Issued Applications
11911
Pending Applications
2
Abandoned Applications
123

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4787900 [patent_doc_number] => 20080141229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'PROCESSOR, PROGRAM CONVERSION APPARATUS, PROGRAM CONVERSION METHOD, AND COMPUTER PROGRAM' [patent_app_type] => utility [patent_app_number] => 11/969083 [patent_app_country] => US [patent_app_date] => 2008-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 25601 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20080141229.pdf [firstpage_image] =>[orig_patent_app_number] => 11969083 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/969083
PROCESSOR, PROGRAM CONVERSION APPARATUS, PROGRAM CONVERSION METHOD, AND COMPUTER PROGRAM Jan 2, 2008 Abandoned
Array ( [id] => 5504310 [patent_doc_number] => 20090164998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'Management of speculative transactions' [patent_app_type] => utility [patent_app_number] => 12/004475 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4620 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20090164998.pdf [firstpage_image] =>[orig_patent_app_number] => 12004475 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/004475
Management of speculative transactions Dec 20, 2007 Issued
Array ( [id] => 4829955 [patent_doc_number] => 20080126751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'SCHEDULER HINT METHOD AND SYSTEM TO IMPROVE NETWORK INTERFACE CONTROLLER (NIC) RECEIVE (RX) PROCESSING CACHE PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 11/945510 [patent_app_country] => US [patent_app_date] => 2007-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7184 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20080126751.pdf [firstpage_image] =>[orig_patent_app_number] => 11945510 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/945510
SCHEDULER HINT METHOD AND SYSTEM TO IMPROVE NETWORK INTERFACE CONTROLLER (NIC) RECEIVE (RX) PROCESSING CACHE PERFORMANCE Nov 26, 2007 Abandoned
Array ( [id] => 9486481 [patent_doc_number] => 08732443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-20 [patent_title] => 'Program processing device and program processing method which is able to control writing into an internal memory' [patent_app_type] => utility [patent_app_number] => 11/935659 [patent_app_country] => US [patent_app_date] => 2007-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3868 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11935659 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/935659
Program processing device and program processing method which is able to control writing into an internal memory Nov 5, 2007 Issued
Array ( [id] => 5305672 [patent_doc_number] => 20090300324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'ARRAY TYPE PROCESSOR AND DATA PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/448809 [patent_app_country] => US [patent_app_date] => 2007-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9787 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20090300324.pdf [firstpage_image] =>[orig_patent_app_number] => 12448809 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/448809
ARRAY TYPE PROCESSOR AND DATA PROCESSING SYSTEM Nov 1, 2007 Abandoned
Array ( [id] => 4735513 [patent_doc_number] => 20080052495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'SYSTEM AND METHOD OF EXECUTION OF REGISTER POINTER INSTRUCTIONS AHEAD OF INSTRUCTION ISSUES' [patent_app_type] => utility [patent_app_number] => 11/924977 [patent_app_country] => US [patent_app_date] => 2007-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4405 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20080052495.pdf [firstpage_image] =>[orig_patent_app_number] => 11924977 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/924977
System and method of execution of register pointer instructions ahead of instruction issues Oct 25, 2007 Issued
Array ( [id] => 5442802 [patent_doc_number] => 20090094441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'Perform Floating Point Operation Instruction' [patent_app_type] => utility [patent_app_number] => 11/868605 [patent_app_country] => US [patent_app_date] => 2007-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9529 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20090094441.pdf [firstpage_image] =>[orig_patent_app_number] => 11868605 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/868605
Executing perform floating point operation instructions Oct 7, 2007 Issued
Array ( [id] => 4441013 [patent_doc_number] => 07971044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Link stack repair of erroneous speculative update' [patent_app_type] => utility [patent_app_number] => 11/867727 [patent_app_country] => US [patent_app_date] => 2007-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4923 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/971/07971044.pdf [firstpage_image] =>[orig_patent_app_number] => 11867727 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/867727
Link stack repair of erroneous speculative update Oct 4, 2007 Issued
Array ( [id] => 4868957 [patent_doc_number] => 20080148016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'MULTIPROCESSOR SYSTEM FOR CONTINUING PROGRAM EXECUTION UPON DETECTION OF ABNORMALITY' [patent_app_type] => utility [patent_app_number] => 11/867941 [patent_app_country] => US [patent_app_date] => 2007-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3085 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20080148016.pdf [firstpage_image] =>[orig_patent_app_number] => 11867941 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/867941
MULTIPROCESSOR SYSTEM FOR CONTINUING PROGRAM EXECUTION UPON DETECTION OF ABNORMALITY Oct 4, 2007 Abandoned
Array ( [id] => 7972125 [patent_doc_number] => 07941641 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-10 [patent_title] => 'Retargetable instruction decoder for a computer processor' [patent_app_type] => utility [patent_app_number] => 11/865624 [patent_app_country] => US [patent_app_date] => 2007-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5471 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/941/07941641.pdf [firstpage_image] =>[orig_patent_app_number] => 11865624 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/865624
Retargetable instruction decoder for a computer processor Sep 30, 2007 Issued
Array ( [id] => 4572652 [patent_doc_number] => 07962724 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-14 [patent_title] => 'Branch loop performance enhancement' [patent_app_type] => utility [patent_app_number] => 11/864579 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4499 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/962/07962724.pdf [firstpage_image] =>[orig_patent_app_number] => 11864579 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/864579
Branch loop performance enhancement Sep 27, 2007 Issued
Array ( [id] => 4804734 [patent_doc_number] => 20080016323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'EARLY ACCESS TO MICROCODE ROM' [patent_app_type] => utility [patent_app_number] => 11/862492 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7203 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20080016323.pdf [firstpage_image] =>[orig_patent_app_number] => 11862492 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/862492
EARLY ACCESS TO MICROCODE ROM Sep 26, 2007 Abandoned
Array ( [id] => 4671629 [patent_doc_number] => 20080046690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'Processor executing SIMD instructions' [patent_app_type] => utility [patent_app_number] => 11/896370 [patent_app_country] => US [patent_app_date] => 2007-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 72 [patent_figures_cnt] => 72 [patent_no_of_words] => 14255 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20080046690.pdf [firstpage_image] =>[orig_patent_app_number] => 11896370 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/896370
Processor executing SIMD instructions Aug 30, 2007 Abandoned
Array ( [id] => 241374 [patent_doc_number] => 07594099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Processor executing SIMD instructions' [patent_app_type] => utility [patent_app_number] => 11/896368 [patent_app_country] => US [patent_app_date] => 2007-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 71 [patent_figures_cnt] => 91 [patent_no_of_words] => 14228 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/594/07594099.pdf [firstpage_image] =>[orig_patent_app_number] => 11896368 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/896368
Processor executing SIMD instructions Aug 30, 2007 Issued
Array ( [id] => 4671627 [patent_doc_number] => 20080046688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'Processor executing SIMD instructions' [patent_app_type] => utility [patent_app_number] => 11/896369 [patent_app_country] => US [patent_app_date] => 2007-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 72 [patent_figures_cnt] => 72 [patent_no_of_words] => 14255 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20080046688.pdf [firstpage_image] =>[orig_patent_app_number] => 11896369 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/896369
Processor executing SIMD instructions Aug 30, 2007 Abandoned
Array ( [id] => 4671643 [patent_doc_number] => 20080046704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'Processor executing SIMD instructions' [patent_app_type] => utility [patent_app_number] => 11/896371 [patent_app_country] => US [patent_app_date] => 2007-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 72 [patent_figures_cnt] => 72 [patent_no_of_words] => 14162 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20080046704.pdf [firstpage_image] =>[orig_patent_app_number] => 11896371 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/896371
Processor executing SIMD instructions Aug 30, 2007 Abandoned
Array ( [id] => 4774100 [patent_doc_number] => 20080059762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'Multi-sequence control for a data parallel system' [patent_app_type] => utility [patent_app_number] => 11/897798 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2799 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20080059762.pdf [firstpage_image] =>[orig_patent_app_number] => 11897798 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/897798
Multi-sequence control for a data parallel system Aug 29, 2007 Abandoned
Array ( [id] => 4854273 [patent_doc_number] => 20080320016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'AGE MATRIX FOR QUEUE DISPATCH ORDER' [patent_app_type] => utility [patent_app_number] => 11/847170 [patent_app_country] => US [patent_app_date] => 2007-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5616 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20080320016.pdf [firstpage_image] =>[orig_patent_app_number] => 11847170 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/847170
AGE MATRIX FOR QUEUE DISPATCH ORDER Aug 28, 2007 Abandoned
Array ( [id] => 4854734 [patent_doc_number] => 20080320478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'AGE MATRIX FOR QUEUE DISPATCH ORDER' [patent_app_type] => utility [patent_app_number] => 11/830727 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5224 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20080320478.pdf [firstpage_image] =>[orig_patent_app_number] => 11830727 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/830727
Age matrix for queue entries dispatch order Jul 29, 2007 Issued
Array ( [id] => 4911302 [patent_doc_number] => 20080022069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'REGISTER FILE REGIONS FOR A PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/829249 [patent_app_country] => US [patent_app_date] => 2007-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5216 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20080022069.pdf [firstpage_image] =>[orig_patent_app_number] => 11829249 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/829249
REGISTER FILE REGIONS FOR A PROCESSING SYSTEM Jul 26, 2007 Abandoned
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