Search

Brian Ngo

Examiner (ID: 19478, Phone: (571)270-7011 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
1309
Issued Applications
1140
Pending Applications
66
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19391715 [patent_doc_number] => 20240281585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => NETWORKING DETECTION METHOD AND SYSTEM [patent_app_type] => utility [patent_app_number] => 18/262198 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 411 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18262198 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/262198
NETWORKING DETECTION METHOD AND SYSTEM Oct 26, 2021 Issued
Array ( [id] => 18843733 [patent_doc_number] => 20230406137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => CHARGE CONTROL DEVICE, CHARGE SYSTEM, CHARGE CONTROL METHOD, AND PROGRAM [patent_app_type] => utility [patent_app_number] => 18/250442 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18250442 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/250442
CHARGE CONTROL DEVICE, CHARGE SYSTEM, CHARGE CONTROL METHOD, AND PROGRAM Oct 26, 2021 Pending
Array ( [id] => 17644355 [patent_doc_number] => 20220172094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => UNDER-RESOLVED QUANTUM-ARRAY STATE MAPPING [patent_app_type] => utility [patent_app_number] => 17/509135 [patent_app_country] => US [patent_app_date] => 2021-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3887 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17509135 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/509135
UNDER-RESOLVED QUANTUM-ARRAY STATE MAPPING Oct 24, 2021 Abandoned
Array ( [id] => 17550637 [patent_doc_number] => 20220121979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => PARAMETER INITIALIZATION ON QUANTUM COMPUTERS THROUGH DOMAIN DECOMPOSITION [patent_app_type] => utility [patent_app_number] => 17/506456 [patent_app_country] => US [patent_app_date] => 2021-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11006 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -42 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17506456 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/506456
Parameter initialization on quantum computers through domain decomposition Oct 19, 2021 Issued
Array ( [id] => 17519968 [patent_doc_number] => 20220105816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => METHOD AND ARRANGEMENT FOR MOUNTING AN ELECTROMAGNETIC CHARGING DEVICE ON A SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/492606 [patent_app_country] => US [patent_app_date] => 2021-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17492606 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/492606
Method and arrangement for mounting an electromagnetic charging device on a substrate Oct 1, 2021 Issued
Array ( [id] => 18711587 [patent_doc_number] => 20230334216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => PHYSICAL VERIFICATION WORKFLOW FOR SEMICONDUCTOR CIRCUIT DESIGNS [patent_app_type] => utility [patent_app_number] => 18/027896 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10037 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18027896 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/027896
Physical verification workflow for semiconductor circuit designs Sep 22, 2021 Issued
Array ( [id] => 20529464 [patent_doc_number] => 12547902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Device and method for neural network computing, and board and readable storage medium [patent_app_type] => utility [patent_app_number] => 18/003682 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 24601 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18003682 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/003682
Device and method for neural network computing, and board and readable storage medium Sep 22, 2021 Issued
Array ( [id] => 18488969 [patent_doc_number] => 20230216319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => BATTERY DISTRIBUTING APPARATUS [patent_app_type] => utility [patent_app_number] => 17/927287 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17927287 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/927287
Battery distributing apparatus Sep 9, 2021 Issued
Array ( [id] => 19703968 [patent_doc_number] => 12198005 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-14 [patent_title] => Quantum computing using multiple quantum computers [patent_app_type] => utility [patent_app_number] => 17/470947 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11303 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470947 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470947
Quantum computing using multiple quantum computers Sep 8, 2021 Issued
Array ( [id] => 19259907 [patent_doc_number] => 12019966 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-06-25 [patent_title] => Virtual isolated pattern layer: isolated pattern recognition, extraction and compression [patent_app_type] => utility [patent_app_number] => 17/466838 [patent_app_country] => US [patent_app_date] => 2021-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17466838 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/466838
Virtual isolated pattern layer: isolated pattern recognition, extraction and compression Sep 2, 2021 Issued
Array ( [id] => 19107699 [patent_doc_number] => 11960808 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-04-16 [patent_title] => Computer-implemented method for deriving resistance, inductance, and capacitive (RLC) values of an RLC equivalent circuit model associated with a fireset [patent_app_type] => utility [patent_app_number] => 17/465250 [patent_app_country] => US [patent_app_date] => 2021-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 14943 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17465250 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/465250
Computer-implemented method for deriving resistance, inductance, and capacitive (RLC) values of an RLC equivalent circuit model associated with a fireset Sep 1, 2021 Issued
Array ( [id] => 19107705 [patent_doc_number] => 11960814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Wafer searching method and device [patent_app_type] => utility [patent_app_number] => 17/463562 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7649 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463562 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463562
Wafer searching method and device Aug 31, 2021 Issued
Array ( [id] => 19228666 [patent_doc_number] => 12008303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Cell overlap violation diagnostics with machine learning [patent_app_type] => utility [patent_app_number] => 17/411876 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8218 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17411876 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/411876
Cell overlap violation diagnostics with machine learning Aug 24, 2021 Issued
Array ( [id] => 18720401 [patent_doc_number] => 11797747 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-24 [patent_title] => Identifying redundant logic based on clock gate enable condition [patent_app_type] => utility [patent_app_number] => 17/410837 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9981 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17410837 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/410837
Identifying redundant logic based on clock gate enable condition Aug 23, 2021 Issued
Array ( [id] => 17430619 [patent_doc_number] => 20220058328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => SYNTHESIS PLACEMENT BOUNDS BASED ON PHYSICAL TIMING ANALYSIS [patent_app_type] => utility [patent_app_number] => 17/408261 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408261 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/408261
Synthesis placement bounds based on physical timing analysis Aug 19, 2021 Issued
Array ( [id] => 19596998 [patent_doc_number] => 12154851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Method of forming a semiconductor device with inter-layer vias [patent_app_type] => utility [patent_app_number] => 17/407969 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5116 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407969 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/407969
Method of forming a semiconductor device with inter-layer vias Aug 19, 2021 Issued
Array ( [id] => 18197873 [patent_doc_number] => 20230051392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => CROSS-HIERARCHY ANTENNA CONDITION VERIFICATION [patent_app_type] => utility [patent_app_number] => 17/402710 [patent_app_country] => US [patent_app_date] => 2021-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17402710 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/402710
Cross-hierarchy antenna condition verification Aug 15, 2021 Issued
Array ( [id] => 18197020 [patent_doc_number] => 20230050539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => HIERARCHICAL COLOR DECOMPOSITION OF PROCESS LAYERS WITH SHAPE AND ORIENTATION REQUIREMENTS [patent_app_type] => utility [patent_app_number] => 17/401441 [patent_app_country] => US [patent_app_date] => 2021-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5861 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17401441 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/401441
Hierarchical color decomposition of process layers with shape and orientation requirements Aug 12, 2021 Issued
Array ( [id] => 19962813 [patent_doc_number] => 12332309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Built-in self-test for network on chip fabric [patent_app_type] => utility [patent_app_number] => 17/399942 [patent_app_country] => US [patent_app_date] => 2021-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12812 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399942 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/399942
Built-in self-test for network on chip fabric Aug 10, 2021 Issued
Array ( [id] => 17276855 [patent_doc_number] => 20210383053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => CHECK TOOL AND CHECK METHOD FOR DESIGN RULE CHECK RULE DECK OF INTEGRATED CIRCUIT LAYOUT [patent_app_type] => utility [patent_app_number] => 17/399107 [patent_app_country] => US [patent_app_date] => 2021-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399107 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/399107
Check tool and check method for design rule check rule deck of integrated circuit layout Aug 10, 2021 Issued
Menu