Search

Brian Ngo

Examiner (ID: 19478, Phone: (571)270-7011 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
1309
Issued Applications
1140
Pending Applications
66
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18007461 [patent_doc_number] => 20220366227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => NEUROMORPHIC DEVICE AND UNIT SYNAPSE DEVICE FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/584302 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17584302 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/584302
NEUROMORPHIC DEVICE AND UNIT SYNAPSE DEVICE FORMING THE SAME Jan 24, 2022 Pending
Array ( [id] => 19719298 [patent_doc_number] => 12204837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Tag coordinate determination method and apparatus, computer-readable medium and electronic device [patent_app_type] => utility [patent_app_number] => 17/648676 [patent_app_country] => US [patent_app_date] => 2022-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648676 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/648676
Tag coordinate determination method and apparatus, computer-readable medium and electronic device Jan 22, 2022 Issued
Array ( [id] => 18592388 [patent_doc_number] => 11741288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Routing-resource-improving method of generating layout diagram, system for same and semiconductor device [patent_app_type] => utility [patent_app_number] => 17/581848 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 14983 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581848 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/581848
Routing-resource-improving method of generating layout diagram, system for same and semiconductor device Jan 20, 2022 Issued
Array ( [id] => 18561934 [patent_doc_number] => 11727180 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-15 [patent_title] => Circuit grouping systems and methods [patent_app_type] => utility [patent_app_number] => 17/578867 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14304 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578867 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/578867
Circuit grouping systems and methods Jan 18, 2022 Issued
Array ( [id] => 19857324 [patent_doc_number] => 12260162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Method and apparatus for printing electrical circuit directly on target surface having 3-dimensional shape, 3D printer used for the same and electrical device having electrical circuit printed by the same [patent_app_type] => utility [patent_app_number] => 17/577081 [patent_app_country] => US [patent_app_date] => 2022-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 5581 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577081 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/577081
Method and apparatus for printing electrical circuit directly on target surface having 3-dimensional shape, 3D printer used for the same and electrical device having electrical circuit printed by the same Jan 16, 2022 Issued
Array ( [id] => 18140178 [patent_doc_number] => 20230014017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => METHOD AND APPARATUS FOR ADJUSTING METAL WIRING DENSITY [patent_app_type] => utility [patent_app_number] => 17/647619 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17647619 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/647619
Method and apparatus for adjusting metal wiring density Jan 10, 2022 Issued
Array ( [id] => 18348903 [patent_doc_number] => 20230137014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => NEURON ELEMENT, DIFFERENTIAL NEURON ELEMENT, A/D CONVERTER AND NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 17/906918 [patent_app_country] => US [patent_app_date] => 2022-01-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17906918 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/906918
NEURON ELEMENT, DIFFERENTIAL NEURON ELEMENT, A/D CONVERTER AND NEURAL NETWORK Dec 31, 2021 Abandoned
Array ( [id] => 19398798 [patent_doc_number] => 12073166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Method and structure for mandrel patterning [patent_app_type] => utility [patent_app_number] => 17/566472 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7411 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566472 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/566472
Method and structure for mandrel patterning Dec 29, 2021 Issued
Array ( [id] => 18954557 [patent_doc_number] => 20240042884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => METHOD AND CIRCUIT FOR PROTECTING AN ON-BOARD CHARGING DEVICE [patent_app_type] => utility [patent_app_number] => 18/258593 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18258593 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/258593
METHOD AND CIRCUIT FOR PROTECTING AN ON-BOARD CHARGING DEVICE Dec 15, 2021 Pending
Array ( [id] => 19811531 [patent_doc_number] => 12242925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Quantum circuit buffering [patent_app_type] => utility [patent_app_number] => 17/551923 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15848 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17551923 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/551923
Quantum circuit buffering Dec 14, 2021 Issued
Array ( [id] => 18872431 [patent_doc_number] => 11860227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Machine learning delay estimation for emulation systems [patent_app_type] => utility [patent_app_number] => 17/548317 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11931 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548317 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/548317
Machine learning delay estimation for emulation systems Dec 9, 2021 Issued
Array ( [id] => 19886065 [patent_doc_number] => 12271783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Control circuit comprising symmetric asymmetric threaded superconducting quantum interference devices (symmetric ATSs) [patent_app_type] => utility [patent_app_number] => 17/547146 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8450 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547146 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/547146
Control circuit comprising symmetric asymmetric threaded superconducting quantum interference devices (symmetric ATSs) Dec 8, 2021 Issued
Array ( [id] => 19626172 [patent_doc_number] => 12165006 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-12-10 [patent_title] => Lattice surgery techniques without using twists [patent_app_type] => utility [patent_app_number] => 17/545906 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 45 [patent_no_of_words] => 14742 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17545906 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/545906
Lattice surgery techniques without using twists Dec 7, 2021 Issued
Array ( [id] => 19069858 [patent_doc_number] => 20240104284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => FEATURE BASED CELL EXTRACTION FOR PATTERN REGIONS [patent_app_type] => utility [patent_app_number] => 18/039701 [patent_app_country] => US [patent_app_date] => 2021-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14578 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18039701 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/039701
FEATURE BASED CELL EXTRACTION FOR PATTERN REGIONS Nov 23, 2021 Pending
Array ( [id] => 17643247 [patent_doc_number] => 20220170985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => DEBUG SYSTEM PROVIDING DEBUG PROTECTION [patent_app_type] => utility [patent_app_number] => 17/534434 [patent_app_country] => US [patent_app_date] => 2021-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3245 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17534434 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/534434
Debug system providing debug protection Nov 22, 2021 Issued
Array ( [id] => 19028275 [patent_doc_number] => 11927627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Systems, methods, and devices for high-speed input/output margin testing [patent_app_type] => utility [patent_app_number] => 17/534404 [patent_app_country] => US [patent_app_date] => 2021-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 13042 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17534404 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/534404
Systems, methods, and devices for high-speed input/output margin testing Nov 22, 2021 Issued
Array ( [id] => 19933971 [patent_doc_number] => 12307176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => System and method for reducing CNOT count in Clifford+T circuits on connectivity constrained architectures [patent_app_type] => utility [patent_app_number] => 17/532273 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 7063 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532273 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532273
System and method for reducing CNOT count in Clifford+T circuits on connectivity constrained architectures Nov 21, 2021 Issued
Array ( [id] => 17629676 [patent_doc_number] => 20220164691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => Methods of Operating Quantum Computing Systems for Amplitude Estimation [patent_app_type] => utility [patent_app_number] => 17/532388 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532388 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532388
Methods of operating quantum computing systems for amplitude estimation Nov 21, 2021 Issued
Array ( [id] => 18390687 [patent_doc_number] => 20230158905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => SNOW PROTECTOR FOR VEHICLE CHARGE PORT [patent_app_type] => utility [patent_app_number] => 17/531232 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531232 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/531232
Snow protector for vehicle charge port Nov 18, 2021 Issued
Array ( [id] => 18331003 [patent_doc_number] => 11636249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Integrated circuit and layout method for standard cell structures [patent_app_type] => utility [patent_app_number] => 17/454004 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9336 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17454004 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/454004
Integrated circuit and layout method for standard cell structures Nov 7, 2021 Issued
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