Search

Brian O Peters

Examiner (ID: 1902, Phone: (571)272-2662 , Office: P/3745 )

Most Active Art Unit
3745
Art Unit(s)
3745
Total Applications
747
Issued Applications
536
Pending Applications
47
Abandoned Applications
164

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16858593 [patent_doc_number] => 20210159338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => SILICON METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR (Si MOSFET) WITH A WIDE-BANDGAP III-V COMPOUND SEMICONDUCTOR GROUP DRAIN AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/007967 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007967 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007967
Silicon metal-oxide-semiconductor field effect transistor (Si MOSFET) with a wide-bandgap III-V compound semiconductor group drain and method for fabricating the same Aug 30, 2020 Issued
Array ( [id] => 17862918 [patent_doc_number] => 11444079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/002392 [patent_app_country] => US [patent_app_date] => 2020-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 19910 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17002392 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/002392
Semiconductor device Aug 24, 2020 Issued
Array ( [id] => 17417270 [patent_doc_number] => 20220052174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => Spacer Structure for Semiconductor Device [patent_app_type] => utility [patent_app_number] => 16/990865 [patent_app_country] => US [patent_app_date] => 2020-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9440 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16990865 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/990865
Spacer structure for semiconductor device Aug 10, 2020 Issued
Array ( [id] => 17189135 [patent_doc_number] => 20210336020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => Backside Vias in Semiconductor Device [patent_app_type] => utility [patent_app_number] => 16/984881 [patent_app_country] => US [patent_app_date] => 2020-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16984881 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/984881
Backside vias in semiconductor device Aug 3, 2020 Issued
Array ( [id] => 17516921 [patent_doc_number] => 11296082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Multi-gate device and related methods [patent_app_type] => utility [patent_app_number] => 16/947377 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 8254 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16947377 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/947377
Multi-gate device and related methods Jul 29, 2020 Issued
Array ( [id] => 17373802 [patent_doc_number] => 20220028854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => TRANSISTORS WITH HYBRID SOURCE/DRAIN REGIONS [patent_app_type] => utility [patent_app_number] => 16/937821 [patent_app_country] => US [patent_app_date] => 2020-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4577 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16937821 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/937821
Transistors with hybrid source/drain regions Jul 23, 2020 Issued
Array ( [id] => 17189149 [patent_doc_number] => 20210336034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => Inner Spacer Features for Multi-Gate Transistors [patent_app_type] => utility [patent_app_number] => 16/937164 [patent_app_country] => US [patent_app_date] => 2020-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8323 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16937164 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/937164
Inner spacer features for multi-gate transistors Jul 22, 2020 Issued
Array ( [id] => 17517026 [patent_doc_number] => 11296187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Seal material for air gaps in semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/937344 [patent_app_country] => US [patent_app_date] => 2020-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 16071 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16937344 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/937344
Seal material for air gaps in semiconductor devices Jul 22, 2020 Issued
Array ( [id] => 17122243 [patent_doc_number] => 11133388 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-28 [patent_title] => Silicon-germanium heterostructures with quantum wells having oscillatory germanium concentration profiles for increased valley splitting [patent_app_type] => utility [patent_app_number] => 16/936697 [patent_app_country] => US [patent_app_date] => 2020-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4379 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16936697 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/936697
Silicon-germanium heterostructures with quantum wells having oscillatory germanium concentration profiles for increased valley splitting Jul 22, 2020 Issued
Array ( [id] => 18137451 [patent_doc_number] => 11563141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Method for attaching ceramic phosphor plates on light-emitting device (LED) dies using a dicing tape, method to form a dicing tape, and dicing tape [patent_app_type] => utility [patent_app_number] => 16/934827 [patent_app_country] => US [patent_app_date] => 2020-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2400 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16934827 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/934827
Method for attaching ceramic phosphor plates on light-emitting device (LED) dies using a dicing tape, method to form a dicing tape, and dicing tape Jul 20, 2020 Issued
Array ( [id] => 16765699 [patent_doc_number] => 20210111281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/934240 [patent_app_country] => US [patent_app_date] => 2020-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13701 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16934240 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/934240
Semiconductor device Jul 20, 2020 Issued
Array ( [id] => 17559323 [patent_doc_number] => 11316046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Method of manufacturing a semiconductor device and a semiconductor device [patent_app_type] => utility [patent_app_number] => 16/933626 [patent_app_country] => US [patent_app_date] => 2020-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 46 [patent_no_of_words] => 11618 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16933626 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/933626
Method of manufacturing a semiconductor device and a semiconductor device Jul 19, 2020 Issued
Array ( [id] => 16677528 [patent_doc_number] => 20210066294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => Uniform Gate Width for Nanostructure Devices [patent_app_type] => utility [patent_app_number] => 16/932476 [patent_app_country] => US [patent_app_date] => 2020-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5699 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16932476 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/932476
Uniform gate width for nanostructure devices Jul 16, 2020 Issued
Array ( [id] => 16888931 [patent_doc_number] => 20210175128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => METHOD OF MAKING 3D CMOS WITH INTEGRATED CHANNEL AND S/D REGIONS [patent_app_type] => utility [patent_app_number] => 16/927462 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927462 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/927462
Method of making 3D CMOS with integrated channel and S/D regions Jul 12, 2020 Issued
Array ( [id] => 17093116 [patent_doc_number] => 11121314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Large height tree-like sub 30nm vias to reduce conductive material re-deposition for sub 60nm MRAM devices [patent_app_type] => utility [patent_app_number] => 16/927461 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2193 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927461 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/927461
Large height tree-like sub 30nm vias to reduce conductive material re-deposition for sub 60nm MRAM devices Jul 12, 2020 Issued
Array ( [id] => 16796056 [patent_doc_number] => 20210125873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/924057 [patent_app_country] => US [patent_app_date] => 2020-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7018 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16924057 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/924057
SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF Jul 7, 2020 Abandoned
Array ( [id] => 16394663 [patent_doc_number] => 20200335604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => SEMICONDUCTOR STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/921019 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16921019 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/921019
Semiconductor structures Jul 5, 2020 Issued
Array ( [id] => 17310325 [patent_doc_number] => 11211452 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-12-28 [patent_title] => Transistor having stacked source/drain regions with formation assistance regions and multi-region wrap-around source/drain contacts [patent_app_type] => utility [patent_app_number] => 16/916736 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9597 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16916736 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/916736
Transistor having stacked source/drain regions with formation assistance regions and multi-region wrap-around source/drain contacts Jun 29, 2020 Issued
Array ( [id] => 17908686 [patent_doc_number] => 11462549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Semiconductor device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 16/916150 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 8467 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16916150 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/916150
Semiconductor device and method of fabricating the same Jun 29, 2020 Issued
Array ( [id] => 16379485 [patent_doc_number] => 20200328328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 16/915579 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16915579 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/915579
Light emitting device and method of manufacturing same Jun 28, 2020 Issued
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