Search

Brian O Peters

Examiner (ID: 1902, Phone: (571)272-2662 , Office: P/3745 )

Most Active Art Unit
3745
Art Unit(s)
3745
Total Applications
747
Issued Applications
536
Pending Applications
47
Abandoned Applications
164

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11869712 [patent_doc_number] => 20170236998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'INTEGRATED ANISOTROPIC MAGNETORESISTIVE DEVICE' [patent_app_type] => utility [patent_app_number] => 15/041575 [patent_app_country] => US [patent_app_date] => 2016-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15041575 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/041575
Integrated anisotropic magnetoresistive device Feb 10, 2016 Issued
Array ( [id] => 11353688 [patent_doc_number] => 20160372428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'Semiconductor Device and Radio Frequency Module Formed on High Resistivity Substrate' [patent_app_type] => utility [patent_app_number] => 15/041535 [patent_app_country] => US [patent_app_date] => 2016-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7353 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15041535 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/041535
Semiconductor device and radio frequency module formed on high resistivity substrate Feb 10, 2016 Issued
Array ( [id] => 11623161 [patent_doc_number] => 20170133349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'METHOD OF PACKAGING INTEGRATED CIRCUIT DIE AND DEVICE' [patent_app_type] => utility [patent_app_number] => 15/041026 [patent_app_country] => US [patent_app_date] => 2016-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15041026 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/041026
Method of packaging integrated circuit die and device Feb 9, 2016 Issued
Array ( [id] => 11432223 [patent_doc_number] => 09570550 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-14 [patent_title] => 'Stacked nanowire semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/988083 [patent_app_country] => US [patent_app_date] => 2016-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 30 [patent_no_of_words] => 3853 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 402 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14988083 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/988083
Stacked nanowire semiconductor device Jan 4, 2016 Issued
Array ( [id] => 10765378 [patent_doc_number] => 20160111534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'DUAL GATE FD-SOI TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/985264 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5871 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14985264 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/985264
Dual gate FD-SOI transistor Dec 29, 2015 Issued
Array ( [id] => 13769779 [patent_doc_number] => 10177239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => HEMT transistor [patent_app_type] => utility [patent_app_number] => 15/535933 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 7530 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15535933 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/535933
HEMT transistor Dec 14, 2015 Issued
Array ( [id] => 12477684 [patent_doc_number] => 09991149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Semiconductor bonding with compliant resin and utilizing hydrogen implantation for transfer-wafer removal [patent_app_type] => utility [patent_app_number] => 14/933694 [patent_app_country] => US [patent_app_date] => 2015-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 8759 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14933694 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/933694
Semiconductor bonding with compliant resin and utilizing hydrogen implantation for transfer-wafer removal Nov 4, 2015 Issued
Array ( [id] => 16575095 [patent_doc_number] => 10897023 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => All quantum dot based optoelectronic device [patent_app_type] => utility [patent_app_number] => 15/765396 [patent_app_country] => US [patent_app_date] => 2015-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15765396 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/765396
All quantum dot based optoelectronic device Oct 1, 2015 Issued
Array ( [id] => 10674126 [patent_doc_number] => 20160020270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-21 [patent_title] => 'METAL-INSULATOR-METAL CAPACITOR, ELECTRONIC DEVICE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/872821 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 14318 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872821 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/872821
METAL-INSULATOR-METAL CAPACITOR, ELECTRONIC DEVICE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME Sep 30, 2015 Abandoned
Array ( [id] => 16187167 [patent_doc_number] => 10720508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-21 [patent_title] => Fabrication of multi-channel nanowire devices with self-aligned internal spacers and SOI FinFETs using selective silicon nitride capping [patent_app_type] => utility [patent_app_number] => 15/750158 [patent_app_country] => US [patent_app_date] => 2015-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10215 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15750158 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/750158
Fabrication of multi-channel nanowire devices with self-aligned internal spacers and SOI FinFETs using selective silicon nitride capping Sep 24, 2015 Issued
Array ( [id] => 11660325 [patent_doc_number] => 09673339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-06 [patent_title] => 'Semiconductor storage device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/839586 [patent_app_country] => US [patent_app_date] => 2015-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 99 [patent_no_of_words] => 23737 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14839586 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/839586
Semiconductor storage device and manufacturing method thereof Aug 27, 2015 Issued
Array ( [id] => 10984336 [patent_doc_number] => 20160181281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'DISPLAY PANEL HAVING IMPROVED BRIGHTNESS AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/813556 [patent_app_country] => US [patent_app_date] => 2015-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 6723 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14813556 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/813556
Display panel having improved brightness and method for fabricating the same Jul 29, 2015 Issued
Array ( [id] => 13201591 [patent_doc_number] => 10115716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Die bonding to a board [patent_app_type] => utility [patent_app_number] => 14/812846 [patent_app_country] => US [patent_app_date] => 2015-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3886 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14812846 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/812846
Die bonding to a board Jul 28, 2015 Issued
Array ( [id] => 10817397 [patent_doc_number] => 20160163559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'METHOD FOR RECESSING A CARBON-DOPED LAYER OF A SEMICONDUCTOR STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/812046 [patent_app_country] => US [patent_app_date] => 2015-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6667 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14812046 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/812046
Method for recessing a carbon-doped layer of a semiconductor structure Jul 28, 2015 Issued
Array ( [id] => 10448051 [patent_doc_number] => 20150333066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-19 [patent_title] => 'FIELD EFFECT TRANSISTOR STRUCTURE HAVING ONE OR MORE FINS' [patent_app_type] => utility [patent_app_number] => 14/810269 [patent_app_country] => US [patent_app_date] => 2015-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5664 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14810269 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/810269
FIELD EFFECT TRANSISTOR STRUCTURE HAVING ONE OR MORE FINS Jul 26, 2015 Abandoned
Array ( [id] => 10426068 [patent_doc_number] => 20150311079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 14/792395 [patent_app_country] => US [patent_app_date] => 2015-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4312 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14792395 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/792395
SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURING METHOD Jul 5, 2015 Abandoned
Array ( [id] => 14153029 [patent_doc_number] => 10256908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Method and system for monolithic integration of photonics and electronics in CMOS processes [patent_app_type] => utility [patent_app_number] => 14/729826 [patent_app_country] => US [patent_app_date] => 2015-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8517 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14729826 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/729826
Method and system for monolithic integration of photonics and electronics in CMOS processes Jun 2, 2015 Issued
Array ( [id] => 10385265 [patent_doc_number] => 20150270272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'Finfet Drive Strength Modification' [patent_app_type] => utility [patent_app_number] => 14/727294 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7614 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14727294 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/727294
Finfet Drive Strength Modification May 31, 2015 Abandoned
Array ( [id] => 12027084 [patent_doc_number] => 20170317183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/513545 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 19040 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15513545 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/513545
Semiconductor device and manufacturing method thereof Mar 29, 2015 Issued
Array ( [id] => 11071413 [patent_doc_number] => 20160268377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'LOW RESISTANCE CONTACT FOR SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 14/656089 [patent_app_country] => US [patent_app_date] => 2015-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4411 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14656089 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/656089
Low resistance contact for semiconductor devices Mar 11, 2015 Issued
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