Search

Brian R. Ohara

Examiner (ID: 17744)

Most Active Art Unit
1724
Art Unit(s)
1724
Total Applications
725
Issued Applications
511
Pending Applications
118
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4973011 [patent_doc_number] => 20070113014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Weak referenced based eviction of persistent data from cache' [patent_app_type] => utility [patent_app_number] => 10/837222 [patent_app_country] => US [patent_app_date] => 2004-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4016 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20070113014.pdf [firstpage_image] =>[orig_patent_app_number] => 10837222 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/837222
Weak referenced based eviction of persistent data from cache Apr 29, 2004 Abandoned
Array ( [id] => 7471563 [patent_doc_number] => 20040199607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'Reconfiguration of storage system including multiple mass storage devices' [patent_app_type] => new [patent_app_number] => 10/826757 [patent_app_country] => US [patent_app_date] => 2004-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 4314 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20040199607.pdf [firstpage_image] =>[orig_patent_app_number] => 10826757 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/826757
Reconfiguration of storage system including multiple mass storage devices Apr 14, 2004 Issued
Array ( [id] => 7091547 [patent_doc_number] => 20050010615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Multi-node computer system implementing memory-correctable speculative proxy transactions' [patent_app_type] => utility [patent_app_number] => 10/821350 [patent_app_country] => US [patent_app_date] => 2004-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 47657 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20050010615.pdf [firstpage_image] =>[orig_patent_app_number] => 10821350 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/821350
Multi-node computer system implementing memory-correctable speculative proxy transactions Apr 8, 2004 Abandoned
Array ( [id] => 7063170 [patent_doc_number] => 20050005075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Multi-node computer system employing multiple memory response states' [patent_app_type] => utility [patent_app_number] => 10/821370 [patent_app_country] => US [patent_app_date] => 2004-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 47614 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20050005075.pdf [firstpage_image] =>[orig_patent_app_number] => 10821370 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/821370
Multi-node computer system employing multiple memory response states Apr 8, 2004 Abandoned
Array ( [id] => 7261959 [patent_doc_number] => 20040260885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Multi-node computer system in which interfaces provide data to satisfy coherency transactions when no owning device present in modified global access state node' [patent_app_type] => new [patent_app_number] => 10/821393 [patent_app_country] => US [patent_app_date] => 2004-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 48010 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20040260885.pdf [firstpage_image] =>[orig_patent_app_number] => 10821393 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/821393
Multi-node computer system in which interfaces provide data to satisfy coherency transactions when no owning device present in modified global access state node Apr 8, 2004 Issued
Array ( [id] => 6953844 [patent_doc_number] => 20050228939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'System and method for optimizing interconnections of components in a multichip memory module' [patent_app_type] => utility [patent_app_number] => 10/822275 [patent_app_country] => US [patent_app_date] => 2004-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5551 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20050228939.pdf [firstpage_image] =>[orig_patent_app_number] => 10822275 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/822275
System and method for optimizing interconnections of components in a multichip memory module Apr 7, 2004 Issued
Array ( [id] => 7112862 [patent_doc_number] => 20050210318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'System and method for drive recovery following a drive failure' [patent_app_type] => utility [patent_app_number] => 10/805811 [patent_app_country] => US [patent_app_date] => 2004-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3829 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20050210318.pdf [firstpage_image] =>[orig_patent_app_number] => 10805811 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/805811
System and method for drive recovery following a drive failure Mar 21, 2004 Abandoned
Array ( [id] => 7262449 [patent_doc_number] => 20050144512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Redundant array of independent disks and conversion method thereof' [patent_app_type] => utility [patent_app_number] => 10/801630 [patent_app_country] => US [patent_app_date] => 2004-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3800 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20050144512.pdf [firstpage_image] =>[orig_patent_app_number] => 10801630 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/801630
Redundant array of independent disks and conversion method thereof Mar 14, 2004 Abandoned
Array ( [id] => 7166814 [patent_doc_number] => 20050086447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Program and apparatus for blocking information leaks, and storage medium for the program' [patent_app_type] => utility [patent_app_number] => 10/793271 [patent_app_country] => US [patent_app_date] => 2004-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7651 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20050086447.pdf [firstpage_image] =>[orig_patent_app_number] => 10793271 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/793271
Program and apparatus for blocking information leaks, and storage medium for the program Mar 4, 2004 Abandoned
Array ( [id] => 7672150 [patent_doc_number] => 20040181629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Information processing apparatus, information processing method and program' [patent_app_type] => new [patent_app_number] => 10/785063 [patent_app_country] => US [patent_app_date] => 2004-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5630 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20040181629.pdf [firstpage_image] =>[orig_patent_app_number] => 10785063 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/785063
Information processing apparatus, information processing method and program Feb 24, 2004 Issued
Array ( [id] => 7052439 [patent_doc_number] => 20050188158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'Cache memory with improved replacement policy' [patent_app_type] => utility [patent_app_number] => 10/786250 [patent_app_country] => US [patent_app_date] => 2004-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6069 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20050188158.pdf [firstpage_image] =>[orig_patent_app_number] => 10786250 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/786250
Cache memory with improved replacement policy Feb 24, 2004 Abandoned
Array ( [id] => 7358628 [patent_doc_number] => 20040250038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Information processing apparatus and memory access arranging method' [patent_app_type] => new [patent_app_number] => 10/764484 [patent_app_country] => US [patent_app_date] => 2004-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7122 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20040250038.pdf [firstpage_image] =>[orig_patent_app_number] => 10764484 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/764484
Information processing apparatus and memory access arranging method Jan 26, 2004 Issued
Array ( [id] => 116439 [patent_doc_number] => 07721062 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-05-18 [patent_title] => 'Method for detecting leaked buffer writes across file system consistency points' [patent_app_type] => utility [patent_app_number] => 10/705470 [patent_app_country] => US [patent_app_date] => 2003-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9785 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/721/07721062.pdf [firstpage_image] =>[orig_patent_app_number] => 10705470 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/705470
Method for detecting leaked buffer writes across file system consistency points Nov 9, 2003 Issued
Array ( [id] => 7259973 [patent_doc_number] => 20050076179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Cache optimized logical partitioning a symmetric multi-processor data processing system' [patent_app_type] => utility [patent_app_number] => 10/677661 [patent_app_country] => US [patent_app_date] => 2003-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5843 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20050076179.pdf [firstpage_image] =>[orig_patent_app_number] => 10677661 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/677661
Cache optimized logical partitioning a symmetric multi-processor data processing system Oct 1, 2003 Abandoned
Array ( [id] => 313049 [patent_doc_number] => 07529885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Cache control method for node apparatus' [patent_app_type] => utility [patent_app_number] => 10/663700 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9427 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 462 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/529/07529885.pdf [firstpage_image] =>[orig_patent_app_number] => 10663700 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/663700
Cache control method for node apparatus Sep 16, 2003 Issued
Array ( [id] => 7085075 [patent_doc_number] => 20050050455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Method and apparatus for supporting object caching in a web presentation architecture' [patent_app_type] => utility [patent_app_number] => 10/652388 [patent_app_country] => US [patent_app_date] => 2003-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5641 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20050050455.pdf [firstpage_image] =>[orig_patent_app_number] => 10652388 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/652388
Method and apparatus for supporting object caching in a web presentation architecture Aug 28, 2003 Abandoned
Array ( [id] => 6968221 [patent_doc_number] => 20050235118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Data storage circuit, data write method in the data storage circuit, and data storage device' [patent_app_type] => utility [patent_app_number] => 10/505431 [patent_app_country] => US [patent_app_date] => 2003-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7006 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20050235118.pdf [firstpage_image] =>[orig_patent_app_number] => 10505431 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/505431
Power saving data storage circuit, data writing method in the same, and data storage device Mar 16, 2003 Issued
Array ( [id] => 469353 [patent_doc_number] => 07240178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'Non-volatile memory and non-volatile memory data rewriting method' [patent_app_type] => utility [patent_app_number] => 10/484322 [patent_app_country] => US [patent_app_date] => 2002-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7592 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/240/07240178.pdf [firstpage_image] =>[orig_patent_app_number] => 10484322 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/484322
Non-volatile memory and non-volatile memory data rewriting method Jul 18, 2002 Issued
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