Search

Brian Turner

Examiner (ID: 13960, Phone: (571)270-5411 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2818
Total Applications
860
Issued Applications
631
Pending Applications
123
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19407412 [patent_doc_number] => 20240290923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/588806 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18588806 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/588806
DISPLAY DEVICE Feb 26, 2024 Pending
Array ( [id] => 19305911 [patent_doc_number] => 20240234491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => VERTICAL SEMICONDUCTOR COMPONENT, IN PARTICULAR VERTICAL TRANSISTOR, WITH MINIMIZED SOURCE-DRAIN LEAKAGE CURRENTS [patent_app_type] => utility [patent_app_number] => 18/402974 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2528 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402974 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402974
VERTICAL SEMICONDUCTOR COMPONENT, IN PARTICULAR VERTICAL TRANSISTOR, WITH MINIMIZED SOURCE-DRAIN LEAKAGE CURRENTS Jan 2, 2024 Pending
Array ( [id] => 19285762 [patent_doc_number] => 20240222239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => SEMICONDUCTOR ELEMENT WITH BONDING LAYER HAVING FUNCTIONAL AND NON-FUNCTIONAL CONDUCTIVE PADS [patent_app_type] => utility [patent_app_number] => 18/395265 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395265 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/395265
SEMICONDUCTOR ELEMENT WITH BONDING LAYER HAVING FUNCTIONAL AND NON-FUNCTIONAL CONDUCTIVE PADS Dec 21, 2023 Pending
Array ( [id] => 19349345 [patent_doc_number] => 20240258309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/519301 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18519301 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/519301
SEMICONDUCTOR DEVICE Nov 26, 2023 Pending
Array ( [id] => 20021661 [patent_doc_number] => 20250159883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 18/516021 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18516021 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/516021
THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF Nov 20, 2023 Pending
Array ( [id] => 20205541 [patent_doc_number] => 12408336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Method for improving control gate uniformity during manufacture of processors with embedded flash memory [patent_app_type] => utility [patent_app_number] => 18/515523 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 1045 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515523 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/515523
Method for improving control gate uniformity during manufacture of processors with embedded flash memory Nov 20, 2023 Issued
Array ( [id] => 19101174 [patent_doc_number] => 20240120402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE INCLUDING FORKSHEET TRANSISTORS AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/513562 [patent_app_country] => US [patent_app_date] => 2023-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14401 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513562 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513562
SEMICONDUCTOR DEVICE STRUCTURE INCLUDING FORKSHEET TRANSISTORS AND METHODS OF FORMING THE SAME Nov 18, 2023 Pending
Array ( [id] => 19305698 [patent_doc_number] => 20240234278 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => INTERCONNECT SUBSTRATE, METHOD OF MAKING THE SAME, AND SEMICONDUCTOR APPARATUS [patent_app_type] => utility [patent_app_number] => 18/489288 [patent_app_country] => US [patent_app_date] => 2023-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18489288 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/489288
INTERCONNECT SUBSTRATE, METHOD OF MAKING THE SAME, AND SEMICONDUCTOR APPARATUS Oct 17, 2023 Pending
Array ( [id] => 19993953 [patent_doc_number] => 20250132175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => ACTIVELY CONTROLLED WINDOW FOR EPITAXIAL DEPOSITION PROCESS TEMPERATURE CONTROL [patent_app_type] => utility [patent_app_number] => 18/489214 [patent_app_country] => US [patent_app_date] => 2023-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18489214 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/489214
ACTIVELY CONTROLLED WINDOW FOR EPITAXIAL DEPOSITION PROCESS TEMPERATURE CONTROL Oct 17, 2023 Pending
Array ( [id] => 19305698 [patent_doc_number] => 20240234278 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => INTERCONNECT SUBSTRATE, METHOD OF MAKING THE SAME, AND SEMICONDUCTOR APPARATUS [patent_app_type] => utility [patent_app_number] => 18/489288 [patent_app_country] => US [patent_app_date] => 2023-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18489288 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/489288
INTERCONNECT SUBSTRATE, METHOD OF MAKING THE SAME, AND SEMICONDUCTOR APPARATUS Oct 16, 2023 Pending
Array ( [id] => 19893363 [patent_doc_number] => 20250118675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => Modular Package of Quantum Hardware [patent_app_type] => utility [patent_app_number] => 18/482843 [patent_app_country] => US [patent_app_date] => 2023-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18482843 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/482843
Modular Package of Quantum Hardware Oct 5, 2023 Pending
Array ( [id] => 19116414 [patent_doc_number] => 20240128164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => INTEGRATED CIRCUIT INCLUDING THROUGH-SILICON VIA AND METHOD OF DESIGNING THE INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/475290 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10381 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475290 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475290
INTEGRATED CIRCUIT INCLUDING THROUGH-SILICON VIA AND METHOD OF DESIGNING THE INTEGRATED CIRCUIT Sep 26, 2023 Pending
Array ( [id] => 18882854 [patent_doc_number] => 20240006223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => METHOD FOR SEMICONDUCTOR DIE EDGE PROTECTION AND SEMICONDUCTOR DIE SEPARATION [patent_app_type] => utility [patent_app_number] => 18/368449 [patent_app_country] => US [patent_app_date] => 2023-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6096 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18368449 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/368449
METHOD FOR SEMICONDUCTOR DIE EDGE PROTECTION AND SEMICONDUCTOR DIE SEPARATION Sep 13, 2023 Pending
Array ( [id] => 19835733 [patent_doc_number] => 20250087519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => BACK GRINDING TAPE HAVING TABS TO ASSIST IN REMOVING THE BACK GRINDING TAPE FROM A WAFER [patent_app_type] => utility [patent_app_number] => 18/464779 [patent_app_country] => US [patent_app_date] => 2023-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18464779 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/464779
BACK GRINDING TAPE HAVING TABS TO ASSIST IN REMOVING THE BACK GRINDING TAPE FROM A WAFER Sep 10, 2023 Pending
Array ( [id] => 19054921 [patent_doc_number] => 20240096890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/460273 [patent_app_country] => US [patent_app_date] => 2023-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18460273 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/460273
SEMICONDUCTOR DEVICE Aug 31, 2023 Pending
Array ( [id] => 18848854 [patent_doc_number] => 20230411258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => SEMICONDUCTOR DEVICE AND CORRESPONDING METHOD [patent_app_type] => utility [patent_app_number] => 18/241414 [patent_app_country] => US [patent_app_date] => 2023-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18241414 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/241414
SEMICONDUCTOR DEVICE AND CORRESPONDING METHOD Aug 31, 2023 Abandoned
Array ( [id] => 19589609 [patent_doc_number] => 20240387166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => SEMICONDUCTOR DEVICE WITH POROUS LAYER AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/240475 [patent_app_country] => US [patent_app_date] => 2023-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18240475 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/240475
SEMICONDUCTOR DEVICE WITH POROUS LAYER AND METHOD FOR FABRICATING THE SAME Aug 30, 2023 Pending
Array ( [id] => 18812522 [patent_doc_number] => 20230386859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => NITRIDE-CONTAINING STI LINER FOR SIGE CHANNEL [patent_app_type] => utility [patent_app_number] => 18/446652 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8667 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446652 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446652
Nitride-containing STI liner for SIGE channel Aug 8, 2023 Issued
Array ( [id] => 19546359 [patent_doc_number] => 20240363395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => METHOD FOR FORMING A SEMICONDUCTOR DEVICE AND DEVICES FABRICATED THEREOF [patent_app_type] => utility [patent_app_number] => 18/231320 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18231320 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/231320
METHOD FOR FORMING A SEMICONDUCTOR DEVICE AND DEVICES FABRICATED THEREOF Aug 7, 2023 Pending
Array ( [id] => 20441472 [patent_doc_number] => 12512314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Processing method of wafer [patent_app_type] => utility [patent_app_number] => 18/366881 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 4823 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366881 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/366881
Processing method of wafer Aug 7, 2023 Issued
Menu