Search

Brian Turner

Examiner (ID: 2043, Phone: (571)270-5411 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2818
Total Applications
877
Issued Applications
648
Pending Applications
113
Abandoned Applications
131

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19515776 [patent_doc_number] => 20240347462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => METHOD FOR FORMING AN INSULATING LAYER PATTERN, PRECURSORS USED IN PATTERN FORMATION AND A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/751201 [patent_app_country] => US [patent_app_date] => 2024-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751201 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/751201
METHOD FOR FORMING AN INSULATING LAYER PATTERN, PRECURSORS USED IN PATTERN FORMATION AND A SEMICONDUCTOR DEVICE Jun 21, 2024 Pending
Array ( [id] => 19575284 [patent_doc_number] => 20240379576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => FLEXIBLE FILAMENT SPLICING STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/655306 [patent_app_country] => US [patent_app_date] => 2024-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8371 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655306 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/655306
FLEXIBLE FILAMENT SPLICING STRUCTURES May 4, 2024 Pending
Array ( [id] => 20326447 [patent_doc_number] => 20250338535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/651253 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18651253 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/651253
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME Apr 29, 2024 Pending
Array ( [id] => 19533892 [patent_doc_number] => 20240357794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => TWO TRANSISTOR CELLS FOR VERTICAL THREE-DIMENSIONAL MEMORY HAVING VERICAL DIGIT LINES [patent_app_type] => utility [patent_app_number] => 18/645043 [patent_app_country] => US [patent_app_date] => 2024-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18645043 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/645043
TWO TRANSISTOR CELLS FOR VERTICAL THREE-DIMENSIONAL MEMORY HAVING VERICAL DIGIT LINES Apr 23, 2024 Pending
Array ( [id] => 19515823 [patent_doc_number] => 20240347509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => SEMICONDUCTOR PACKAGE STRIP AND METHOD FOR FORMING A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/636301 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18636301 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/636301
SEMICONDUCTOR PACKAGE STRIP AND METHOD FOR FORMING A SEMICONDUCTOR DEVICE Apr 15, 2024 Pending
Array ( [id] => 19500476 [patent_doc_number] => 20240339494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => VERTICAL MOSFET WITH HIGH SHORT CIRCUIT WITHSTAND TIME CAPABILITY [patent_app_type] => utility [patent_app_number] => 18/625100 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625100 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625100
VERTICAL MOSFET WITH HIGH SHORT CIRCUIT WITHSTAND TIME CAPABILITY Apr 1, 2024 Pending
Array ( [id] => 20283692 [patent_doc_number] => 20250308934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => SELECTIVE DEFLASH PROCESS FOR LEAD FRAMES [patent_app_type] => utility [patent_app_number] => 18/622966 [patent_app_country] => US [patent_app_date] => 2024-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18622966 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/622966
SELECTIVE DEFLASH PROCESS FOR LEAD FRAMES Mar 30, 2024 Pending
Array ( [id] => 19407412 [patent_doc_number] => 20240290923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/588806 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18588806 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/588806
DISPLAY DEVICE Feb 26, 2024 Pending
Array ( [id] => 19454955 [patent_doc_number] => 20240315085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => MOTHER SUBSTRATE FOR DISPLAY DEVICE, DISPLAY DEVICE AND MANUFACTURING METHOD OF DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/582879 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9688 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18582879 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/582879
MOTHER SUBSTRATE FOR DISPLAY DEVICE, DISPLAY DEVICE AND MANUFACTURING METHOD OF DISPLAY DEVICE Feb 20, 2024 Pending
Array ( [id] => 19305911 [patent_doc_number] => 20240234491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => VERTICAL SEMICONDUCTOR COMPONENT, IN PARTICULAR VERTICAL TRANSISTOR, WITH MINIMIZED SOURCE-DRAIN LEAKAGE CURRENTS [patent_app_type] => utility [patent_app_number] => 18/402974 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2528 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402974 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402974
VERTICAL SEMICONDUCTOR COMPONENT, IN PARTICULAR VERTICAL TRANSISTOR, WITH MINIMIZED SOURCE-DRAIN LEAKAGE CURRENTS Jan 2, 2024 Pending
Array ( [id] => 19285762 [patent_doc_number] => 20240222239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => SEMICONDUCTOR ELEMENT WITH BONDING LAYER HAVING FUNCTIONAL AND NON-FUNCTIONAL CONDUCTIVE PADS [patent_app_type] => utility [patent_app_number] => 18/395265 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395265 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/395265
SEMICONDUCTOR ELEMENT WITH BONDING LAYER HAVING FUNCTIONAL AND NON-FUNCTIONAL CONDUCTIVE PADS Dec 21, 2023 Pending
Array ( [id] => 19054836 [patent_doc_number] => 20240096805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => SEMICONDUCTOR DEVICES WITH BACKSIDE ROUTING AND METHOD OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 18/526445 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17718 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18526445 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/526445
SEMICONDUCTOR DEVICES WITH BACKSIDE ROUTING AND METHOD OF FORMING SAME Nov 30, 2023 Pending
Array ( [id] => 19349345 [patent_doc_number] => 20240258309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/519301 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18519301 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/519301
SEMICONDUCTOR DEVICE Nov 26, 2023 Pending
Array ( [id] => 20205541 [patent_doc_number] => 12408336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Method for improving control gate uniformity during manufacture of processors with embedded flash memory [patent_app_type] => utility [patent_app_number] => 18/515523 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 1045 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515523 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/515523
Method for improving control gate uniformity during manufacture of processors with embedded flash memory Nov 20, 2023 Issued
Array ( [id] => 20021661 [patent_doc_number] => 20250159883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 18/516021 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18516021 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/516021
THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF Nov 20, 2023 Pending
Array ( [id] => 19101174 [patent_doc_number] => 20240120402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE INCLUDING FORKSHEET TRANSISTORS AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/513562 [patent_app_country] => US [patent_app_date] => 2023-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14401 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513562 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513562
SEMICONDUCTOR DEVICE STRUCTURE INCLUDING FORKSHEET TRANSISTORS AND METHODS OF FORMING THE SAME Nov 18, 2023 Pending
Array ( [id] => 19993953 [patent_doc_number] => 20250132175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => ACTIVELY CONTROLLED WINDOW FOR EPITAXIAL DEPOSITION PROCESS TEMPERATURE CONTROL [patent_app_type] => utility [patent_app_number] => 18/489214 [patent_app_country] => US [patent_app_date] => 2023-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18489214 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/489214
ACTIVELY CONTROLLED WINDOW FOR EPITAXIAL DEPOSITION PROCESS TEMPERATURE CONTROL Oct 17, 2023 Pending
Array ( [id] => 19305698 [patent_doc_number] => 20240234278 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => INTERCONNECT SUBSTRATE, METHOD OF MAKING THE SAME, AND SEMICONDUCTOR APPARATUS [patent_app_type] => utility [patent_app_number] => 18/489288 [patent_app_country] => US [patent_app_date] => 2023-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18489288 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/489288
INTERCONNECT SUBSTRATE, METHOD OF MAKING THE SAME, AND SEMICONDUCTOR APPARATUS Oct 17, 2023 Pending
Array ( [id] => 19305698 [patent_doc_number] => 20240234278 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => INTERCONNECT SUBSTRATE, METHOD OF MAKING THE SAME, AND SEMICONDUCTOR APPARATUS [patent_app_type] => utility [patent_app_number] => 18/489288 [patent_app_country] => US [patent_app_date] => 2023-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18489288 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/489288
INTERCONNECT SUBSTRATE, METHOD OF MAKING THE SAME, AND SEMICONDUCTOR APPARATUS Oct 16, 2023 Pending
Array ( [id] => 19893363 [patent_doc_number] => 20250118675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => Modular Package of Quantum Hardware [patent_app_type] => utility [patent_app_number] => 18/482843 [patent_app_country] => US [patent_app_date] => 2023-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18482843 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/482843
Modular Package of Quantum Hardware Oct 5, 2023 Pending
Menu