Search

Brian Turner

Examiner (ID: 4389, Phone: (571)270-5411 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2818
Total Applications
860
Issued Applications
632
Pending Applications
120
Abandoned Applications
131

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18631981 [patent_doc_number] => 20230290886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 17/790885 [patent_app_country] => US [patent_app_date] => 2021-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4056 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17790885 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/790885
Semiconductor structures and manufacturing methods thereof Apr 14, 2021 Issued
Array ( [id] => 17765037 [patent_doc_number] => 20220238650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => SELECTIVE LOW TEMPERATURE EPITAXIAL DEPOSITION PROCESS [patent_app_type] => utility [patent_app_number] => 17/231087 [patent_app_country] => US [patent_app_date] => 2021-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17231087 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/231087
Selective low temperature epitaxial deposition process Apr 14, 2021 Issued
Array ( [id] => 16995383 [patent_doc_number] => 20210233803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => METHOD FOR FORMING SEMICONDUCTOR DIE HAVING EDGE WITH MULTIPLE GRADIENTS [patent_app_type] => utility [patent_app_number] => 17/231163 [patent_app_country] => US [patent_app_date] => 2021-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17231163 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/231163
Method for forming semiconductor die having edge with multiple gradients Apr 14, 2021 Issued
Array ( [id] => 19828853 [patent_doc_number] => 12249649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/207751 [patent_app_country] => US [patent_app_date] => 2021-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3888 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207751 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/207751
Semiconductor device Mar 21, 2021 Issued
Array ( [id] => 17738228 [patent_doc_number] => 20220223690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => Method of Forming Fully Strained Channels [patent_app_type] => utility [patent_app_number] => 17/207058 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9292 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207058 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/207058
Method of forming fully strained channels Mar 18, 2021 Issued
Array ( [id] => 18874877 [patent_doc_number] => 11862700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Semiconductor device structure including forksheet transistors and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/207573 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 14514 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207573 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/207573
Semiconductor device structure including forksheet transistors and methods of forming the same Mar 18, 2021 Issued
Array ( [id] => 17886458 [patent_doc_number] => 20220301936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => Nanosheet Device with Different Gate Lengths in Same Stack [patent_app_type] => utility [patent_app_number] => 17/203489 [patent_app_country] => US [patent_app_date] => 2021-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12946 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17203489 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/203489
Nanosheet device with different gate lengths in same stack Mar 15, 2021 Issued
Array ( [id] => 16936597 [patent_doc_number] => 20210202486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => SEMICONDUCTOR DEVICE HAVING HYBRID CAPACITORS [patent_app_type] => utility [patent_app_number] => 17/201121 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6988 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17201121 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/201121
Semiconductor device having hybrid capacitors Mar 14, 2021 Issued
Array ( [id] => 17115842 [patent_doc_number] => 20210296439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/202237 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13396 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17202237 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/202237
Method of manufacturing a semiconductor device and a semiconductor device Mar 14, 2021 Issued
Array ( [id] => 18440265 [patent_doc_number] => 20230187560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => SEMICONDUCTOR DEVICE HAVING ZIGZAG STRUCTURE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/998456 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -38 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17998456 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/998456
Semiconductor device having zigzag structure, method of manufacturing semiconductor device, and electronic device Mar 10, 2021 Issued
Array ( [id] => 17855448 [patent_doc_number] => 20220285491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => TRANSISTOR SOURCE/DRAIN EPITAXY BLOCKER [patent_app_type] => utility [patent_app_number] => 17/189755 [patent_app_country] => US [patent_app_date] => 2021-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6440 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17189755 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/189755
TRANSISTOR SOURCE/DRAIN EPITAXY BLOCKER Mar 1, 2021 Abandoned
Array ( [id] => 17840711 [patent_doc_number] => 20220278017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => Power Electronics Carrier [patent_app_type] => utility [patent_app_number] => 17/186224 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17186224 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/186224
Power electronics carrier Feb 25, 2021 Issued
Array ( [id] => 18857546 [patent_doc_number] => 11855143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Semiconductor structures and methods thereof [patent_app_type] => utility [patent_app_number] => 17/187458 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 37 [patent_no_of_words] => 10880 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187458 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/187458
Semiconductor structures and methods thereof Feb 25, 2021 Issued
Array ( [id] => 17840696 [patent_doc_number] => 20220278002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => METHOD FOR FORMING EPITAXIAL SOURCE/DRAIN FEATURES USING A SELF-ALIGNED MASK AND SEMICONDUCTOR DEVICES FABRICATED THEREOF [patent_app_type] => utility [patent_app_number] => 17/187283 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187283 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/187283
Method for forming epitaxial source/drain features using a self-aligned mask and semiconductor devices fabricated thereof Feb 25, 2021 Issued
Array ( [id] => 17833867 [patent_doc_number] => 20220271171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => NANOSHEET SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/184245 [patent_app_country] => US [patent_app_date] => 2021-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184245 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184245
Nanosheet semiconductor device and method for manufacturing the same Feb 23, 2021 Issued
Array ( [id] => 18248941 [patent_doc_number] => 11605537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-14 [patent_title] => Integrated circuits with doped gate dielectrics [patent_app_type] => utility [patent_app_number] => 17/181970 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7762 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181970 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/181970
Integrated circuits with doped gate dielectrics Feb 21, 2021 Issued
Array ( [id] => 19766044 [patent_doc_number] => 12224347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => P-type field effect transistor (PFET) on a silicon germanium (Ge) buffer layer to increase Ge in the PFET source and drain to increase compression of the PFET channel and method of fabrication [patent_app_type] => utility [patent_app_number] => 17/180219 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8819 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17180219 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/180219
P-type field effect transistor (PFET) on a silicon germanium (Ge) buffer layer to increase Ge in the PFET source and drain to increase compression of the PFET channel and method of fabrication Feb 18, 2021 Issued
Array ( [id] => 17893278 [patent_doc_number] => 11456260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-27 [patent_title] => Wafer processing method [patent_app_type] => utility [patent_app_number] => 17/171213 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 29 [patent_no_of_words] => 12238 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171213 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/171213
Wafer processing method Feb 8, 2021 Issued
Array ( [id] => 18277113 [patent_doc_number] => 11616062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Gate isolation for multigate device [patent_app_type] => utility [patent_app_number] => 17/170740 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 30 [patent_no_of_words] => 29933 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17170740 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/170740
Gate isolation for multigate device Feb 7, 2021 Issued
Array ( [id] => 18073882 [patent_doc_number] => 11532724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Selective gate spacers for semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/154755 [patent_app_country] => US [patent_app_date] => 2021-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 13125 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17154755 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/154755
Selective gate spacers for semiconductor devices Jan 20, 2021 Issued
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