Search

Brian Turner

Examiner (ID: 4389, Phone: (571)270-5411 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2818
Total Applications
860
Issued Applications
632
Pending Applications
120
Abandoned Applications
131

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17196175 [patent_doc_number] => 11164942 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-02 [patent_title] => Method for forming nanosheet transistor structures [patent_app_type] => utility [patent_app_number] => 16/885040 [patent_app_country] => US [patent_app_date] => 2020-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 7391 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16885040 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/885040
Method for forming nanosheet transistor structures May 26, 2020 Issued
Array ( [id] => 17941707 [patent_doc_number] => 11476166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Nano-sheet-based complementary metal-oxide-semiconductor devices with asymmetric inner spacers [patent_app_type] => utility [patent_app_number] => 16/875726 [patent_app_country] => US [patent_app_date] => 2020-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 34 [patent_no_of_words] => 15288 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16875726 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/875726
Nano-sheet-based complementary metal-oxide-semiconductor devices with asymmetric inner spacers May 14, 2020 Issued
Array ( [id] => 16936867 [patent_doc_number] => 20210202756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => NANOSTRUCTURE FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING [patent_app_type] => utility [patent_app_number] => 15/931717 [patent_app_country] => US [patent_app_date] => 2020-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15931717 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/931717
Nanostructure field-effect transistor device and method of forming May 13, 2020 Issued
Array ( [id] => 16440368 [patent_doc_number] => 20200357695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => WAFER PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 16/870353 [patent_app_country] => US [patent_app_date] => 2020-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16870353 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/870353
Wafer processing method May 7, 2020 Issued
Array ( [id] => 16440369 [patent_doc_number] => 20200357696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => WAFER PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 16/870395 [patent_app_country] => US [patent_app_date] => 2020-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8391 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16870395 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/870395
Wafer processing method May 7, 2020 Issued
Array ( [id] => 17217844 [patent_doc_number] => 20210351182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => APPARATUSES INCLUDING TRANSISTORS, AND RELATED METHODS, MEMORY DEVICES, AND ELECTRONIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/869339 [patent_app_country] => US [patent_app_date] => 2020-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14509 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16869339 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/869339
Apparatuses including transistors, and related methods, memory devices, and electronic systems May 6, 2020 Issued
Array ( [id] => 17217938 [patent_doc_number] => 20210351276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => FIELD EFFECT TRANSISTOR (FET) COMPRISING INNER SPACERS AND VOIDS BETWEEN CHANNELS [patent_app_type] => utility [patent_app_number] => 16/868376 [patent_app_country] => US [patent_app_date] => 2020-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15395 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16868376 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/868376
Field effect transistor (FET) comprising inner spacers and voids between channels May 5, 2020 Issued
Array ( [id] => 16759901 [patent_doc_number] => 10978458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Semiconductor device including ultra low-k spacer and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 16/866760 [patent_app_country] => US [patent_app_date] => 2020-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 11796 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16866760 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/866760
Semiconductor device including ultra low-k spacer and method for fabricating the same May 4, 2020 Issued
Array ( [id] => 16257013 [patent_doc_number] => 20200266388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/865673 [patent_app_country] => US [patent_app_date] => 2020-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16865673 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/865673
Display device May 3, 2020 Issued
Array ( [id] => 16625007 [patent_doc_number] => 20210043660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => METHOD FOR PREPARING INTERLAYER INSULATING LAYER AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, THIN FILM TRANSISTOR [patent_app_type] => utility [patent_app_number] => 16/862865 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16862865 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/862865
Method for preparing interlayer insulating layer and method for manufacturing thin film transistor, thin film transistor Apr 29, 2020 Issued
Array ( [id] => 16773898 [patent_doc_number] => 10985019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Method of forming a semiconductor device using layered etching and repairing of damaged portions [patent_app_type] => utility [patent_app_number] => 16/859822 [patent_app_country] => US [patent_app_date] => 2020-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 6254 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16859822 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/859822
Method of forming a semiconductor device using layered etching and repairing of damaged portions Apr 26, 2020 Issued
Array ( [id] => 17825864 [patent_doc_number] => 11430819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Array substrate and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/761913 [patent_app_country] => US [patent_app_date] => 2020-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4671 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16761913 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/761913
Array substrate and manufacturing method thereof Apr 23, 2020 Issued
Array ( [id] => 16226173 [patent_doc_number] => 20200251290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => MATERIAL PROPERTY CAPACITANCE SENSOR [patent_app_type] => utility [patent_app_number] => 16/853219 [patent_app_country] => US [patent_app_date] => 2020-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14284 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16853219 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/853219
Material property capacitance sensor Apr 19, 2020 Issued
Array ( [id] => 16226438 [patent_doc_number] => 20200251555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/853616 [patent_app_country] => US [patent_app_date] => 2020-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13369 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16853616 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/853616
Method of manufacturing a semiconductor device and a semiconductor device Apr 19, 2020 Issued
Array ( [id] => 16394461 [patent_doc_number] => 20200335402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/851645 [patent_app_country] => US [patent_app_date] => 2020-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16851645 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/851645
SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF Apr 16, 2020 Abandoned
Array ( [id] => 16471630 [patent_doc_number] => 20200373168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => FORMATION OF BOTTOM ISOLATION [patent_app_type] => utility [patent_app_number] => 16/850265 [patent_app_country] => US [patent_app_date] => 2020-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11128 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16850265 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/850265
Formation of bottom isolation Apr 15, 2020 Issued
Array ( [id] => 17971327 [patent_doc_number] => 11488875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Semiconductor substrate measuring apparatus and plasma treatment apparatus using the same [patent_app_type] => utility [patent_app_number] => 16/847727 [patent_app_country] => US [patent_app_date] => 2020-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 6100 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16847727 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/847727
Semiconductor substrate measuring apparatus and plasma treatment apparatus using the same Apr 13, 2020 Issued
Array ( [id] => 17623170 [patent_doc_number] => 11342234 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Semiconductor device and nonvolatile memory device including crack detection structure [patent_app_type] => utility [patent_app_number] => 16/846724 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 33 [patent_no_of_words] => 11823 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16846724 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/846724
Semiconductor device and nonvolatile memory device including crack detection structure Apr 12, 2020 Issued
Array ( [id] => 16379375 [patent_doc_number] => 20200328218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/845641 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5288 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845641 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/845641
Semiconductor structure and fabrication method thereof Apr 9, 2020 Issued
Array ( [id] => 16194315 [patent_doc_number] => 20200235164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => NOVEL RESISTIVE RANDOM ACCESS MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/843635 [patent_app_country] => US [patent_app_date] => 2020-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16843635 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/843635
Resistive random access memory device Apr 7, 2020 Issued
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