Search

Brian Turner

Examiner (ID: 4389, Phone: (571)270-5411 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2818
Total Applications
860
Issued Applications
632
Pending Applications
120
Abandoned Applications
131

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17730834 [patent_doc_number] => 11387236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/840880 [patent_app_country] => US [patent_app_date] => 2020-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 9934 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16840880 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/840880
Semiconductor device Apr 5, 2020 Issued
Array ( [id] => 16372661 [patent_doc_number] => 10804427 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Method of manufacturing light-emitting element [patent_app_type] => utility [patent_app_number] => 16/837150 [patent_app_country] => US [patent_app_date] => 2020-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6005 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 380 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16837150 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/837150
Method of manufacturing light-emitting element Mar 31, 2020 Issued
Array ( [id] => 17818714 [patent_doc_number] => 11424338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Metal source/drain features [patent_app_type] => utility [patent_app_number] => 16/836320 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9025 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16836320 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/836320
Metal source/drain features Mar 30, 2020 Issued
Array ( [id] => 17130326 [patent_doc_number] => 20210305095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => METHOD FOR FORMING A PACKAGED SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/828115 [patent_app_country] => US [patent_app_date] => 2020-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4408 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16828115 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/828115
METHOD FOR FORMING A PACKAGED SEMICONDUCTOR DEVICE Mar 23, 2020 Abandoned
Array ( [id] => 17803479 [patent_doc_number] => 11417792 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-16 [patent_title] => Interconnect with nanotube fitting [patent_app_type] => utility [patent_app_number] => 16/824567 [patent_app_country] => US [patent_app_date] => 2020-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 31 [patent_no_of_words] => 17822 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16824567 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/824567
Interconnect with nanotube fitting Mar 18, 2020 Issued
Array ( [id] => 17107402 [patent_doc_number] => 11127628 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-21 [patent_title] => Semiconductor device with connecting structure having a step-shaped conductive feature and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 16/820267 [patent_app_country] => US [patent_app_date] => 2020-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 11255 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16820267 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/820267
Semiconductor device with connecting structure having a step-shaped conductive feature and method for fabricating the same Mar 15, 2020 Issued
Array ( [id] => 17100217 [patent_doc_number] => 20210288008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => Method Of Manufacturing An Augmented LED Array Assembly [patent_app_type] => utility [patent_app_number] => 16/814024 [patent_app_country] => US [patent_app_date] => 2020-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16814024 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/814024
Method of manufacturing an augmented LED array assembly Mar 9, 2020 Issued
Array ( [id] => 17085715 [patent_doc_number] => 20210280722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => STRAINED SILICON TRANSISTOR [patent_app_type] => utility [patent_app_number] => 16/809534 [patent_app_country] => US [patent_app_date] => 2020-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5046 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16809534 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/809534
STRAINED SILICON TRANSISTOR Mar 3, 2020 Abandoned
Array ( [id] => 17070881 [patent_doc_number] => 20210273098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => Semiconductor Device and Method [patent_app_type] => utility [patent_app_number] => 16/803278 [patent_app_country] => US [patent_app_date] => 2020-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17585 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16803278 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/803278
Semiconductor device and method Feb 26, 2020 Issued
Array ( [id] => 17978807 [patent_doc_number] => 11495682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Semiconductor device and method [patent_app_type] => utility [patent_app_number] => 16/802873 [patent_app_country] => US [patent_app_date] => 2020-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 40 [patent_no_of_words] => 10638 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16802873 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/802873
Semiconductor device and method Feb 26, 2020 Issued
Array ( [id] => 17772465 [patent_doc_number] => 11404417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Low leakage device [patent_app_type] => utility [patent_app_number] => 16/802311 [patent_app_country] => US [patent_app_date] => 2020-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 36 [patent_no_of_words] => 10456 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16802311 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/802311
Low leakage device Feb 25, 2020 Issued
Array ( [id] => 17224748 [patent_doc_number] => 11177258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Stacked nanosheet CFET with gate all around structure [patent_app_type] => utility [patent_app_number] => 16/798316 [patent_app_country] => US [patent_app_date] => 2020-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 9993 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16798316 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/798316
Stacked nanosheet CFET with gate all around structure Feb 21, 2020 Issued
Array ( [id] => 16370419 [patent_doc_number] => 10802169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Determining node depth and water column transit velocity [patent_app_type] => utility [patent_app_number] => 16/790272 [patent_app_country] => US [patent_app_date] => 2020-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10489 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 411 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16790272 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/790272
Determining node depth and water column transit velocity Feb 12, 2020 Issued
Array ( [id] => 17745592 [patent_doc_number] => 11393672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Methods of forming microelectronic devices including an interdeck region between deck structures [patent_app_type] => utility [patent_app_number] => 16/789168 [patent_app_country] => US [patent_app_date] => 2020-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 12962 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16789168 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/789168
Methods of forming microelectronic devices including an interdeck region between deck structures Feb 11, 2020 Issued
Array ( [id] => 17956419 [patent_doc_number] => 11482533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Apparatus and methods for plug fill deposition in 3-D NAND applications [patent_app_type] => utility [patent_app_number] => 16/789138 [patent_app_country] => US [patent_app_date] => 2020-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 3203 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16789138 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/789138
Apparatus and methods for plug fill deposition in 3-D NAND applications Feb 11, 2020 Issued
Array ( [id] => 17332355 [patent_doc_number] => 11222823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Wafer processing method [patent_app_type] => utility [patent_app_number] => 16/781458 [patent_app_country] => US [patent_app_date] => 2020-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 10386 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16781458 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/781458
Wafer processing method Feb 3, 2020 Issued
Array ( [id] => 16001165 [patent_doc_number] => 20200176453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => SEMICONDUCTOR STRUCTURE WITH CAPACITOR LANDING PAD AND METHOD OF MAKE THE SAME [patent_app_type] => utility [patent_app_number] => 16/779670 [patent_app_country] => US [patent_app_date] => 2020-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16779670 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/779670
SEMICONDUCTOR STRUCTURE WITH CAPACITOR LANDING PAD AND METHOD OF MAKE THE SAME Feb 2, 2020 Abandoned
Array ( [id] => 15969781 [patent_doc_number] => 20200168642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => LASER IRRADIATION DEVICE, PROJECTION MASK, LASER IRRADIATION METHOD, AND PROGRAM [patent_app_type] => utility [patent_app_number] => 16/779978 [patent_app_country] => US [patent_app_date] => 2020-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6795 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16779978 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/779978
LASER IRRADIATION DEVICE, PROJECTION MASK, LASER IRRADIATION METHOD, AND PROGRAM Feb 2, 2020 Abandoned
Array ( [id] => 17254119 [patent_doc_number] => 11189617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Gate-all-around devices with reduced parasitic capacitance [patent_app_type] => utility [patent_app_number] => 16/774278 [patent_app_country] => US [patent_app_date] => 2020-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6410 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16774278 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/774278
Gate-all-around devices with reduced parasitic capacitance Jan 27, 2020 Issued
Array ( [id] => 16995489 [patent_doc_number] => 20210233909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => FLEXIBLE GAA NANOSHEET HEIGHT AND CHANNEL MATERIALS [patent_app_type] => utility [patent_app_number] => 16/751371 [patent_app_country] => US [patent_app_date] => 2020-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7473 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16751371 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/751371
FLEXIBLE GAA NANOSHEET HEIGHT AND CHANNEL MATERIALS Jan 23, 2020 Abandoned
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