Search

Brian Turner

Examiner (ID: 2043, Phone: (571)270-5411 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2818
Total Applications
877
Issued Applications
648
Pending Applications
113
Abandoned Applications
131

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17863040 [patent_doc_number] => 11444202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Semiconductor device and method of forming the same [patent_app_type] => utility [patent_app_number] => 16/745340 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 8668 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16745340 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/745340
Semiconductor device and method of forming the same Jan 16, 2020 Issued
Array ( [id] => 16966195 [patent_doc_number] => 20210217694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => Memory Arrays And Methods Used In Forming A Memory Array [patent_app_type] => utility [patent_app_number] => 16/743329 [patent_app_country] => US [patent_app_date] => 2020-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6854 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16743329 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/743329
Memory arrays and methods used in forming a memory array Jan 14, 2020 Issued
Array ( [id] => 16819890 [patent_doc_number] => 11004728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Semiconductor die having edge with multiple gradients and method for forming the same [patent_app_type] => utility [patent_app_number] => 16/741078 [patent_app_country] => US [patent_app_date] => 2020-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7835 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741078 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/741078
Semiconductor die having edge with multiple gradients and method for forming the same Jan 12, 2020 Issued
Array ( [id] => 17332354 [patent_doc_number] => 11222822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Workpiece cutting method [patent_app_type] => utility [patent_app_number] => 16/738210 [patent_app_country] => US [patent_app_date] => 2020-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 9321 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16738210 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/738210
Workpiece cutting method Jan 8, 2020 Issued
Array ( [id] => 17500774 [patent_doc_number] => 11289484 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Forming source and drain regions for sheet transistors [patent_app_type] => utility [patent_app_number] => 16/733852 [patent_app_country] => US [patent_app_date] => 2020-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 5815 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16733852 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/733852
Forming source and drain regions for sheet transistors Jan 2, 2020 Issued
Array ( [id] => 18088801 [patent_doc_number] => 11538940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Semiconductor device and electronic device [patent_app_type] => utility [patent_app_number] => 16/728423 [patent_app_country] => US [patent_app_date] => 2019-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 124 [patent_no_of_words] => 35042 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16728423 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/728423
Semiconductor device and electronic device Dec 26, 2019 Issued
Array ( [id] => 16936469 [patent_doc_number] => 20210202358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => Fan-Out Packages and Methods of Forming the Same [patent_app_type] => utility [patent_app_number] => 16/727159 [patent_app_country] => US [patent_app_date] => 2019-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12188 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727159 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/727159
Fan-out packages and methods of forming the same Dec 25, 2019 Issued
Array ( [id] => 18562970 [patent_doc_number] => 11728223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Semiconductor device and methods of manufacture [patent_app_type] => utility [patent_app_number] => 16/723218 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 37 [patent_no_of_words] => 12484 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16723218 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/723218
Semiconductor device and methods of manufacture Dec 19, 2019 Issued
Array ( [id] => 15807693 [patent_doc_number] => 20200126989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => FinFET Devices with Dummy Fins Having Multiple Dielectric Layers [patent_app_type] => utility [patent_app_number] => 16/721220 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16721220 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/721220
FinFET devices with dummy fins having multiple dielectric layers Dec 18, 2019 Issued
Array ( [id] => 16653303 [patent_doc_number] => 10930495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Integrated circuits with doped gate dielectrics [patent_app_type] => utility [patent_app_number] => 16/719290 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7747 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16719290 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/719290
Integrated circuits with doped gate dielectrics Dec 17, 2019 Issued
Array ( [id] => 16487953 [patent_doc_number] => 20200381562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/715431 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715431 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/715431
Semiconductor devices Dec 15, 2019 Issued
Array ( [id] => 16536522 [patent_doc_number] => 10879135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Overlay error and process window metrology [patent_app_type] => utility [patent_app_number] => 16/715892 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9096 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715892 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/715892
Overlay error and process window metrology Dec 15, 2019 Issued
Array ( [id] => 15775993 [patent_doc_number] => 20200119014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => Semiconductor Device and Fabricating the Same [patent_app_type] => utility [patent_app_number] => 16/711501 [patent_app_country] => US [patent_app_date] => 2019-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16711501 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/711501
Semiconductor device and fabricating the same Dec 11, 2019 Issued
Array ( [id] => 15775841 [patent_doc_number] => 20200118938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => Semiconductor Device With Shield for Electromagnetic Interference [patent_app_type] => utility [patent_app_number] => 16/710142 [patent_app_country] => US [patent_app_date] => 2019-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16710142 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/710142
Semiconductor device with shield for electromagnetic interference Dec 10, 2019 Issued
Array ( [id] => 17402844 [patent_doc_number] => 20220044935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 17/413605 [patent_app_country] => US [patent_app_date] => 2019-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17413605 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/413605
Substrate processing apparatus and substrate processing method Dec 8, 2019 Issued
Array ( [id] => 16487702 [patent_doc_number] => 20200381311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/707118 [patent_app_country] => US [patent_app_date] => 2019-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9775 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16707118 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/707118
Semiconductor device and method of fabricating the same Dec 8, 2019 Issued
Array ( [id] => 16471648 [patent_doc_number] => 20200373186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => WAFER BONDING APPARATUSES [patent_app_type] => utility [patent_app_number] => 16/703062 [patent_app_country] => US [patent_app_date] => 2019-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16703062 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/703062
Wafer bonding apparatuses Dec 3, 2019 Issued
Array ( [id] => 17145471 [patent_doc_number] => 20210313484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => METHOD FOR AUTOMATIC FILM EXPANSION, STORAGE MEDIUM, AND DEVICE [patent_app_type] => utility [patent_app_number] => 17/055910 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3959 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17055910 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/055910
Method for automatic film expansion, storage medium, and device Dec 1, 2019 Issued
Array ( [id] => 15873433 [patent_doc_number] => 20200144120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE WITH METAL FILM [patent_app_type] => utility [patent_app_number] => 16/671463 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16671463 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/671463
Manufacturing method of semiconductor device with metal film Oct 31, 2019 Issued
Array ( [id] => 16471705 [patent_doc_number] => 20200373243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/671625 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7301 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16671625 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/671625
Semiconductor package and method of manufacturing the semiconductor package Oct 31, 2019 Issued
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