Search

Brian Turner

Examiner (ID: 4389, Phone: (571)270-5411 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2818
Total Applications
860
Issued Applications
632
Pending Applications
120
Abandoned Applications
131

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16637951 [patent_doc_number] => 10916466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Wafer uniting method [patent_app_type] => utility [patent_app_number] => 16/539481 [patent_app_country] => US [patent_app_date] => 2019-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5343 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16539481 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/539481
Wafer uniting method Aug 12, 2019 Issued
Array ( [id] => 16631609 [patent_doc_number] => 20210050262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => HYBRID WAFER DICING APPROACH USING AN ACTIVELY-FOCUSED LASER BEAM LASER SCRIBING PROCESS AND PLASMA ETCH PROCESS [patent_app_type] => utility [patent_app_number] => 16/539828 [patent_app_country] => US [patent_app_date] => 2019-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8450 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16539828 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/539828
Hybrid wafer dicing approach using an actively-focused laser beam laser scribing process and plasma etch process Aug 12, 2019 Issued
Array ( [id] => 16617467 [patent_doc_number] => 20210036120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => FINFET SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/526756 [patent_app_country] => US [patent_app_date] => 2019-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6018 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16526756 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/526756
FinFET semiconductor device Jul 29, 2019 Issued
Array ( [id] => 16617474 [patent_doc_number] => 20210036127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => DEVICE PERFORMANCE BY FLUORINE TREATMENT [patent_app_type] => utility [patent_app_number] => 16/526650 [patent_app_country] => US [patent_app_date] => 2019-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16526650 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/526650
Device performance by fluorine treatment Jul 29, 2019 Issued
Array ( [id] => 15154847 [patent_doc_number] => 20190355901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => METHOD OF CLEANING A SUBSTRATE PROCESSING APPARATUS AND THE SUBSTRATE PROCESSING APPARATUS PERFORMING THE METHOD [patent_app_type] => utility [patent_app_number] => 16/526165 [patent_app_country] => US [patent_app_date] => 2019-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6422 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16526165 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/526165
Method of cleaning a substrate processing apparatus and the substrate processing apparatus performing the method Jul 29, 2019 Issued
Array ( [id] => 17032779 [patent_doc_number] => 11094597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Structure and formation method of semiconductor device with fin structures [patent_app_type] => utility [patent_app_number] => 16/526692 [patent_app_country] => US [patent_app_date] => 2019-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 36 [patent_no_of_words] => 8736 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16526692 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/526692
Structure and formation method of semiconductor device with fin structures Jul 29, 2019 Issued
Array ( [id] => 16973534 [patent_doc_number] => 11069514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Remote capacitively coupled plasma source with improved ion blocker [patent_app_type] => utility [patent_app_number] => 16/523241 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4381 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523241 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/523241
Remote capacitively coupled plasma source with improved ion blocker Jul 25, 2019 Issued
Array ( [id] => 15442565 [patent_doc_number] => 20200035466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 16/523034 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9753 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523034 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/523034
Substrate processing apparatus and substrate processing control method Jul 25, 2019 Issued
Array ( [id] => 15370043 [patent_doc_number] => 20200020786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/517220 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16517220 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/517220
Selective gate spacers for semiconductor devices Jul 18, 2019 Issued
Array ( [id] => 15041619 [patent_doc_number] => 20190331814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => Amplitude-versus-angle Analysis for Quantitative Interpretation [patent_app_type] => utility [patent_app_number] => 16/509009 [patent_app_country] => US [patent_app_date] => 2019-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7243 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16509009 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/509009
Amplitude-versus-angle analysis for quantitative interpretation Jul 10, 2019 Issued
Array ( [id] => 17289037 [patent_doc_number] => 11205597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Semiconductor device and method [patent_app_type] => utility [patent_app_number] => 16/458437 [patent_app_country] => US [patent_app_date] => 2019-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 44 [patent_no_of_words] => 11496 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458437 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/458437
Semiconductor device and method Jun 30, 2019 Issued
Array ( [id] => 15717887 [patent_doc_number] => 20200105711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => LITHOGRAPHY PROCESS FOR SEMICONDUCTOR PACKAGING AND STRUCTURES RESULTING THEREFROM [patent_app_type] => utility [patent_app_number] => 16/459218 [patent_app_country] => US [patent_app_date] => 2019-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16459218 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/459218
Lithography process for semiconductor packaging and structures resulting therefrom Jun 30, 2019 Issued
Array ( [id] => 16560420 [patent_doc_number] => 20210005569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => GANG CLIP [patent_app_type] => utility [patent_app_number] => 16/459033 [patent_app_country] => US [patent_app_date] => 2019-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16459033 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/459033
GANG CLIP Jun 30, 2019 Abandoned
Array ( [id] => 17092891 [patent_doc_number] => 11121089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Integrated circuit package and method [patent_app_type] => utility [patent_app_number] => 16/458960 [patent_app_country] => US [patent_app_date] => 2019-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 11231 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458960 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/458960
Integrated circuit package and method Jun 30, 2019 Issued
Array ( [id] => 15841235 [patent_doc_number] => 20200135900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => FinFET Device and Method of Forming Same [patent_app_type] => utility [patent_app_number] => 16/458571 [patent_app_country] => US [patent_app_date] => 2019-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13284 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458571 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/458571
FinFET device and method of forming same Jun 30, 2019 Issued
Array ( [id] => 15299709 [patent_doc_number] => 20190392990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => Multilayer Device Having An Improved Antiferromagnetic Pinning Layer And A Corresponding Manufacturing Method [patent_app_type] => utility [patent_app_number] => 16/449567 [patent_app_country] => US [patent_app_date] => 2019-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16449567 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/449567
Multilayer device having an improved antiferromagnetic pinning layer and a corresponding manufacturing method Jun 23, 2019 Issued
Array ( [id] => 16132307 [patent_doc_number] => 10699921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => Semiconductor processing chamber multistage mixing apparatus [patent_app_type] => utility [patent_app_number] => 16/448323 [patent_app_country] => US [patent_app_date] => 2019-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8925 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16448323 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/448323
Semiconductor processing chamber multistage mixing apparatus Jun 20, 2019 Issued
Array ( [id] => 16528911 [patent_doc_number] => 20200402992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE CONTAINING THROUGH-ARRAY CONTACT VIA STRUCTURES BETWEEN DIELECTRIC BARRIER WALLS AND METHODS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/444125 [patent_app_country] => US [patent_app_date] => 2019-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26696 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16444125 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/444125
Three-dimensional memory device containing through-array contact via structures between dielectric barrier walls and methods of making the same Jun 17, 2019 Issued
Array ( [id] => 15274521 [patent_doc_number] => 20190385995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-19 [patent_title] => INTEGRATED CIRCUIT COMPRISING MACROS AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/443441 [patent_app_country] => US [patent_app_date] => 2019-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6481 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16443441 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/443441
Integrated circuit comprising macros and method of fabricating the same Jun 16, 2019 Issued
Array ( [id] => 17818531 [patent_doc_number] => 11424153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Back grinding tape [patent_app_type] => utility [patent_app_number] => 16/964364 [patent_app_country] => US [patent_app_date] => 2019-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4390 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16964364 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/964364
Back grinding tape Jun 3, 2019 Issued
Menu