Brian Turner

Array ( [id] => 11517611 [patent_doc_number] => 20170084685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/367126 [patent_app_country] => US [patent_app_date] => 2016-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2782 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15367126 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12019883 [patent_doc_number] => 09812595 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-07 [patent_title] => 'All-wavelength (VIS-LWIR) transparent electrical contacts and interconnects and methods of making them' [patent_app_type] => utility [patent_app_number] => 15/359532 [patent_app_country] => US [patent_app_date] => 2016-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 38 [patent_no_of_words] => 5784 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15359532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11666243 [patent_doc_number] => 20170154963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'CONTROLLED DOPING FROM LOW TO HIGH LEVELS IN WIDE BANDGAP SEMICONDUCTORS' [patent_app_type] => utility [patent_app_number] => 15/349323 [patent_app_country] => US [patent_app_date] => 2016-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15349323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12089029 [patent_doc_number] => 09842762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-12 [patent_title] => 'Method of manufacturing a semiconductor wafer having an SOI configuration' [patent_app_type] => utility [patent_app_number] => 15/349306 [patent_app_country] => US [patent_app_date] => 2016-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6938 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15349306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12738619 [patent_doc_number] => 20180138040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => SELF-ALIGNED MULTI-PATTERNING PROCESS FLOW WITH ALD GAPFILL SPACER MASK [patent_app_type] => utility [patent_app_number] => 15/349746 [patent_app_country] => US [patent_app_date] => 2016-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15349746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11760214 [patent_doc_number] => 20170207083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'METHODS OF FORMING A LOW-K DIELECTRIC LAYER AND METHODS OF FABRICATING A SEMICONDUCTOR DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/349359 [patent_app_country] => US [patent_app_date] => 2016-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12945 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15349359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11630785 [patent_doc_number] => 20170140973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'LAMINATE BODY AND COMPOSITE BODY; SEMICONDUCTOR DEVICE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 15/349169 [patent_app_country] => US [patent_app_date] => 2016-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6789 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15349169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11630758 [patent_doc_number] => 20170140948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'SEMICONDUCTOR PACKAGE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 15/349855 [patent_app_country] => US [patent_app_date] => 2016-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8859 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15349855 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12739375 [patent_doc_number] => 20180138292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => METHODS AND APPARATUS FOR THREE-DIMENSIONAL NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 15/349382 [patent_app_country] => US [patent_app_date] => 2016-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15349382 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11631065 [patent_doc_number] => 20170141254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'PASSIVATED CONTACT FORMATION USING ION IMPLANTATION' [patent_app_type] => utility [patent_app_number] => 15/349630 [patent_app_country] => US [patent_app_date] => 2016-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5342 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15349630 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11632684 [patent_doc_number] => 20170142874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'METHOD AND APPARATUS FOR USE IN THE MANUFACTURE OF A DISPLAY ELEMENT' [patent_app_type] => utility [patent_app_number] => 15/349760 [patent_app_country] => US [patent_app_date] => 2016-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4625 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15349760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11630784 [patent_doc_number] => 20170140974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'LAMINATED BODY AND COMPOSITE BODY; ASSEMBLY RETRIEVAL METHOD; AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 15/349172 [patent_app_country] => US [patent_app_date] => 2016-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7688 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15349172 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15015731 [patent_doc_number] => 10454029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Method for reducing the wet etch rate of a sin film without damaging the underlying substrate [patent_app_type] => utility [patent_app_number] => 15/349753 [patent_app_country] => US [patent_app_date] => 2016-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10413 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15349753 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11630783 [patent_doc_number] => 20170140972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'LAMINATED BODY AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 15/349154 [patent_app_country] => US [patent_app_date] => 2016-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10047 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15349154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12738754 [patent_doc_number] => 20180138085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => SELECTIVE COBALT REMOVAL FOR BOTTOM UP GAPFILL [patent_app_type] => utility [patent_app_number] => 15/349460 [patent_app_country] => US [patent_app_date] => 2016-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8414 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15349460 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14301215 [patent_doc_number] => 10290741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Thin film transistor, array substrate and display panel having the same, and fabricating method thereof [patent_app_type] => utility [patent_app_number] => 15/529682 [patent_app_country] => US [patent_app_date] => 2016-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 7991 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15529682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14526373 [patent_doc_number] => 10340458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Perovskite hybrid solar cells [patent_app_type] => utility [patent_app_number] => 15/339501 [patent_app_country] => US [patent_app_date] => 2016-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 38 [patent_no_of_words] => 10850 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15339501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12954049 [patent_doc_number] => 09837497 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-05 [patent_title] => Channel structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/296045 [patent_app_country] => US [patent_app_date] => 2016-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4845 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15296045 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12650520 [patent_doc_number] => 20180108671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE WITH LEAKAGE REDUCING SUPPORT PILLAR STRUCTURES AND METHOD OF MAKING THEREOF [patent_app_type] => utility [patent_app_number] => 15/296380 [patent_app_country] => US [patent_app_date] => 2016-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15296380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11593009 [patent_doc_number] => 20170117421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 15/296339 [patent_app_country] => US [patent_app_date] => 2016-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9027 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15296339 [rel_patent_id] =>[rel_patent_doc_number] =>)