Search

Brian Turner

Examiner (ID: 2043, Phone: (571)270-5411 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2818
Total Applications
877
Issued Applications
648
Pending Applications
113
Abandoned Applications
131

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10570339 [patent_doc_number] => 09293517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-22 [patent_title] => 'Array substrate and manufacturing method thereof, and display panel' [patent_app_type] => utility [patent_app_number] => 14/550173 [patent_app_country] => US [patent_app_date] => 2014-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5930 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14550173 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/550173
Array substrate and manufacturing method thereof, and display panel Nov 20, 2014 Issued
Array ( [id] => 10802836 [patent_doc_number] => 20160148993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'REDUCING DIRECT SOURCE-TO-DRAIN TUNNELING IN FIELD EFFECT TRANSISTORS WITH LOW EFFECTIVE MASS CHANNELS' [patent_app_type] => utility [patent_app_number] => 14/550350 [patent_app_country] => US [patent_app_date] => 2014-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14550350 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/550350
Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels Nov 20, 2014 Issued
Array ( [id] => 10800803 [patent_doc_number] => 20160146960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'METHOD OF ANALYSING A SUBSURFACE REGION' [patent_app_type] => utility [patent_app_number] => 14/549672 [patent_app_country] => US [patent_app_date] => 2014-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9204 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14549672 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/549672
METHOD OF ANALYSING A SUBSURFACE REGION Nov 20, 2014 Abandoned
Array ( [id] => 10531058 [patent_doc_number] => 09257198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Shift register unit, shift register, gate drive circuit and display apparatus' [patent_app_type] => utility [patent_app_number] => 14/548920 [patent_app_country] => US [patent_app_date] => 2014-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6717 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14548920 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/548920
Shift register unit, shift register, gate drive circuit and display apparatus Nov 19, 2014 Issued
Array ( [id] => 10802835 [patent_doc_number] => 20160148992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/548298 [patent_app_country] => US [patent_app_date] => 2014-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2578 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14548298 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/548298
Semiconductor device Nov 19, 2014 Issued
Array ( [id] => 11360235 [patent_doc_number] => 09536893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Three-dimensional memory and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/541169 [patent_app_country] => US [patent_app_date] => 2014-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 1922 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14541169 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/541169
Three-dimensional memory and method for manufacturing the same Nov 13, 2014 Issued
Array ( [id] => 11802495 [patent_doc_number] => 09543401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => '3D semiconductor integrated circuit device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/540866 [patent_app_country] => US [patent_app_date] => 2014-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3507 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14540866 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/540866
3D semiconductor integrated circuit device and method of manufacturing the same Nov 12, 2014 Issued
Array ( [id] => 10674125 [patent_doc_number] => 20160020271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-21 [patent_title] => 'SUBSTRATE WITH CRYSTALLIZED SILICON FILM AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/539738 [patent_app_country] => US [patent_app_date] => 2014-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4451 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14539738 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/539738
Substrate with crystallized silicon film and manufacturing method thereof Nov 11, 2014 Issued
Array ( [id] => 10394851 [patent_doc_number] => 20150279857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/539140 [patent_app_country] => US [patent_app_date] => 2014-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 12776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14539140 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/539140
Semiconductor device and method of fabricating the same Nov 11, 2014 Issued
Array ( [id] => 12935839 [patent_doc_number] => 09831171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-28 [patent_title] => Capacitors with barrier dielectric layers, and methods of formation thereof [patent_app_type] => utility [patent_app_number] => 14/539557 [patent_app_country] => US [patent_app_date] => 2014-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 4682 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14539557 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/539557
Capacitors with barrier dielectric layers, and methods of formation thereof Nov 11, 2014 Issued
Array ( [id] => 11279700 [patent_doc_number] => 09496182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-15 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 14/539175 [patent_app_country] => US [patent_app_date] => 2014-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5627 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14539175 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/539175
Semiconductor device and method for fabricating the same Nov 11, 2014 Issued
Array ( [id] => 11739040 [patent_doc_number] => 09703623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-11 [patent_title] => 'Adjusting the use of a chip/socket having a damaged pin' [patent_app_type] => utility [patent_app_number] => 14/538216 [patent_app_country] => US [patent_app_date] => 2014-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6687 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14538216 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/538216
Adjusting the use of a chip/socket having a damaged pin Nov 10, 2014 Issued
Array ( [id] => 10409923 [patent_doc_number] => 20150294932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'SEMICONDUCTOR PACKAGE SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/537657 [patent_app_country] => US [patent_app_date] => 2014-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3892 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14537657 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/537657
SEMICONDUCTOR PACKAGE SUBSTRATE Nov 9, 2014 Abandoned
Array ( [id] => 10394662 [patent_doc_number] => 20150279669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'METHOD OF PREPARING ZnO NANOWIRE AND ZnO NANOWIRE PREPARED THEREBY' [patent_app_type] => utility [patent_app_number] => 14/537207 [patent_app_country] => US [patent_app_date] => 2014-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4473 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14537207 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/537207
Method of preparing ZnO nanowire and ZnO nanowire prepared thereby Nov 9, 2014 Issued
Array ( [id] => 11807331 [patent_doc_number] => 09548415 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-17 [patent_title] => 'All-wavelength (VIS-LWIR) transparent electrical contacts and interconnects and methods of making them' [patent_app_type] => utility [patent_app_number] => 14/530365 [patent_app_country] => US [patent_app_date] => 2014-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 38 [patent_no_of_words] => 5749 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14530365 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/530365
All-wavelength (VIS-LWIR) transparent electrical contacts and interconnects and methods of making them Oct 30, 2014 Issued
Array ( [id] => 10252379 [patent_doc_number] => 20150137375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'COPPER WIRE AND DIELECTRIC WITH AIR GAPS' [patent_app_type] => utility [patent_app_number] => 14/526741 [patent_app_country] => US [patent_app_date] => 2014-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4757 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14526741 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/526741
Copper wire and dielectric with air gaps Oct 28, 2014 Issued
Array ( [id] => 10486993 [patent_doc_number] => 20150372013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/522651 [patent_app_country] => US [patent_app_date] => 2014-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5786 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14522651 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/522651
Array substrate, manufacturing method thereof, and display device Oct 23, 2014 Issued
Array ( [id] => 10772098 [patent_doc_number] => 20160118255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-28 [patent_title] => 'METHODS OF FORMING STRAINED EPITAXIAL SEMICONDUCTOR MATERIAL(S) ABOVE A STRAIN-RELAXED BUFFER LAYER' [patent_app_type] => utility [patent_app_number] => 14/523334 [patent_app_country] => US [patent_app_date] => 2014-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4557 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14523334 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/523334
Methods of forming strained epitaxial semiconductor material(S) above a strain-relaxed buffer layer Oct 23, 2014 Issued
Array ( [id] => 11536358 [patent_doc_number] => 09610751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-04 [patent_title] => 'Display device having cushion pad' [patent_app_type] => utility [patent_app_number] => 14/523022 [patent_app_country] => US [patent_app_date] => 2014-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4768 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14523022 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/523022
Display device having cushion pad Oct 23, 2014 Issued
Array ( [id] => 11286463 [patent_doc_number] => 09502322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-22 [patent_title] => 'Molding compound supported RDL for IC package' [patent_app_type] => utility [patent_app_number] => 14/522760 [patent_app_country] => US [patent_app_date] => 2014-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 41 [patent_no_of_words] => 2377 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14522760 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/522760
Molding compound supported RDL for IC package Oct 23, 2014 Issued
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