Search

Brian Turner

Examiner (ID: 2043, Phone: (571)270-5411 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2818
Total Applications
877
Issued Applications
648
Pending Applications
113
Abandoned Applications
131

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19130947 [patent_doc_number] => 20240136300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => OVERLAY MARK FORMING MOIRE PATTERN, OVERLAY MEASUREMENT METHOD USING SAME, OVERLAY MEASUREMENT APPARATUS USING SAME, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING SAME [patent_app_type] => utility [patent_app_number] => 18/312177 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312177 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312177
Overlay mark forming Moire pattern, overlay measurement method using same, overlay measurement apparatus using same, and manufacturing method of semiconductor device using same May 3, 2023 Issued
Array ( [id] => 19546688 [patent_doc_number] => 20240363724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/307025 [patent_app_country] => US [patent_app_date] => 2023-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18307025 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/307025
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Apr 25, 2023 Pending
Array ( [id] => 19531998 [patent_doc_number] => 20240355900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/302010 [patent_app_country] => US [patent_app_date] => 2023-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7298 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18302010 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/302010
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Apr 17, 2023 Pending
Array ( [id] => 18570592 [patent_doc_number] => 20230260929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => ELECTRONIC COMPONENT MODULE [patent_app_type] => utility [patent_app_number] => 18/301322 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8504 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301322 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/301322
ELECTRONIC COMPONENT MODULE Apr 16, 2023 Pending
Array ( [id] => 19886877 [patent_doc_number] => 12272606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/300983 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 8811 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18300983 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/300983
Semiconductor device Apr 13, 2023 Issued
Array ( [id] => 19515850 [patent_doc_number] => 20240347536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/299663 [patent_app_country] => US [patent_app_date] => 2023-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8328 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18299663 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/299663
INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME Apr 11, 2023 Abandoned
Array ( [id] => 19146313 [patent_doc_number] => 20240145343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => CELL ARCHITECTURE WITH CENTER-LINE POWER RAILS FOR STACKED FIELD-EFFECT TRANSISTORS [patent_app_type] => utility [patent_app_number] => 18/133872 [patent_app_country] => US [patent_app_date] => 2023-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9104 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18133872 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/133872
CELL ARCHITECTURE WITH CENTER-LINE POWER RAILS FOR STACKED FIELD-EFFECT TRANSISTORS Apr 11, 2023 Pending
Array ( [id] => 18812617 [patent_doc_number] => 20230386954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => WAFER LEVEL CHIP SCALE PACKAGE WITH SIDEWALL PROTECTION [patent_app_type] => utility [patent_app_number] => 18/132437 [patent_app_country] => US [patent_app_date] => 2023-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2178 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18132437 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/132437
WAFER LEVEL CHIP SCALE PACKAGE WITH SIDEWALL PROTECTION Apr 9, 2023 Pending
Array ( [id] => 18743574 [patent_doc_number] => 20230352562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/296511 [patent_app_country] => US [patent_app_date] => 2023-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18296511 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/296511
SEMICONDUCTOR DEVICE Apr 5, 2023 Pending
Array ( [id] => 19485247 [patent_doc_number] => 20240333289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => METHOD AND SYSTEM FOR HARDENING A TRANSISTOR LOGIC GATE [patent_app_type] => utility [patent_app_number] => 18/193861 [patent_app_country] => US [patent_app_date] => 2023-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5803 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18193861 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/193861
METHOD AND SYSTEM FOR HARDENING A TRANSISTOR LOGIC GATE Mar 30, 2023 Pending
Array ( [id] => 18570661 [patent_doc_number] => 20230260998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => GATE ISOLATION FOR MULTIGATE DEVICE [patent_app_type] => utility [patent_app_number] => 18/190657 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29971 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18190657 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/190657
Gate isolation for multigate device Mar 26, 2023 Issued
Array ( [id] => 18696574 [patent_doc_number] => 20230327015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/122153 [patent_app_country] => US [patent_app_date] => 2023-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18122153 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/122153
SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF Mar 15, 2023 Pending
Array ( [id] => 19101011 [patent_doc_number] => 20240120239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => MULTI-GATE DEVICE FABRICATION METHODS AND RELATED STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/181750 [patent_app_country] => US [patent_app_date] => 2023-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18181750 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/181750
Multi-gate device fabrication methods and related structures Mar 9, 2023 Issued
Array ( [id] => 18789622 [patent_doc_number] => 20230378320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => EPITAXIAL FEATURES IN SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/181173 [patent_app_country] => US [patent_app_date] => 2023-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13368 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18181173 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/181173
Epitaxial features in semiconductor devices and manufacturing method thereof Mar 8, 2023 Issued
Array ( [id] => 20484000 [patent_doc_number] => 12532479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Semiconductor device having ferroelectric memory cells and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/179720 [patent_app_country] => US [patent_app_date] => 2023-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 1197 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18179720 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/179720
Semiconductor device having ferroelectric memory cells and method of manufacturing the same Mar 6, 2023 Issued
Array ( [id] => 18906162 [patent_doc_number] => 20240021647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => IMAGE SENSING DEVICE INCLUDING THROUGH SILICON VIA (TSV) STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/177625 [patent_app_country] => US [patent_app_date] => 2023-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18177625 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/177625
Image sensing device including through silicon via (TSV) structure Mar 1, 2023 Issued
Array ( [id] => 19191643 [patent_doc_number] => 20240170556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/171524 [patent_app_country] => US [patent_app_date] => 2023-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18171524 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/171524
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME Feb 19, 2023 Pending
Array ( [id] => 18615769 [patent_doc_number] => 20230282508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => MODIFIED SEMICONDUCTOR DIE CARRIER AND CARRIER TAPE [patent_app_type] => utility [patent_app_number] => 18/111424 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18111424 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/111424
MODIFIED SEMICONDUCTOR DIE CARRIER AND CARRIER TAPE Feb 16, 2023 Pending
Array ( [id] => 19071189 [patent_doc_number] => 20240105615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => FIELD-EFFECT TRANSISTOR WITH UNIFORM SOURCE/DRAIN REGIONS ON SELF-ALIGNED DIRECT BACKSIDE CONTACT STRUCTURES OF BACKSIDE POWER DISTRIBUTION NETWORK (BSPDN) [patent_app_type] => utility [patent_app_number] => 18/110296 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110296 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/110296
FIELD-EFFECT TRANSISTOR WITH UNIFORM SOURCE/DRAIN REGIONS ON SELF-ALIGNED DIRECT BACKSIDE CONTACT STRUCTURES OF BACKSIDE POWER DISTRIBUTION NETWORK (BSPDN) Feb 14, 2023 Pending
Array ( [id] => 20691863 [patent_doc_number] => 12622035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/107793 [patent_app_country] => US [patent_app_date] => 2023-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 64 [patent_no_of_words] => 7810 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18107793 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/107793
Semiconductor devices Feb 8, 2023 Issued
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