Brian W. Brown

Array ( [id] => 20152101 [patent_doc_number] => 20250251939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => BUNDLING AND DYNAMIC ALLOCATION OF REGISTER BLOCKS FOR VECTOR INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 19/044169 [patent_app_country] => US [patent_app_date] => 2025-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2261 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19044169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19878614 [patent_doc_number] => 20250110871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => ENHANCEMENTS TO DATAGEN ALGORITHM TO GAIN ADDITIONAL PERFORMANCE FOR L1 DATASET [patent_app_type] => utility [patent_app_number] => 18/980082 [patent_app_country] => US [patent_app_date] => 2024-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18980082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20070799 [patent_doc_number] => 20250209021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => SCALABLE I/O VIRTUALIZATION INTERRUPT AND SCHEDULING [patent_app_type] => utility [patent_app_number] => 18/967216 [patent_app_country] => US [patent_app_date] => 2024-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 51003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18967216 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20018137 [patent_doc_number] => 20250156359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => Apparatus for connecting at least two secondary devices to one port of a master [patent_app_type] => utility [patent_app_number] => 18/944503 [patent_app_country] => US [patent_app_date] => 2024-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18944503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19891909 [patent_doc_number] => 20250117221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => SYSTEMS, METHODS, AND APPARATUSES FOR TILE TRANSPOSE [patent_app_type] => utility [patent_app_number] => 18/920691 [patent_app_country] => US [patent_app_date] => 2024-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18920691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19747921 [patent_doc_number] => 20250036486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => DATA RACE DETECTION METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 18/917040 [patent_app_country] => US [patent_app_date] => 2024-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18917040 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20520364 [patent_doc_number] => 20260044472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-12 [patent_title] => SYSTEMS AND METHODS FOR OPERATING A SERIAL PERIPHERAL INTERFACE (SPI) NETWORK [patent_app_type] => utility [patent_app_number] => 18/915445 [patent_app_country] => US [patent_app_date] => 2024-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1116 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18915445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19892040 [patent_doc_number] => 20250117352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => ACCELERATION UNIT WITH MODULAR ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/910202 [patent_app_country] => US [patent_app_date] => 2024-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12432 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18910202 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19892036 [patent_doc_number] => 20250117348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => METHOD FOR AUTOMATICALLY ASSIGNING IDENTIFIERS TO CONTROLLED NODES OF A FIELDBUS NETWORK [patent_app_type] => utility [patent_app_number] => 18/904463 [patent_app_country] => US [patent_app_date] => 2024-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4218 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18904463 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20529138 [patent_doc_number] => 12547574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => I/O carrier and backplane for industrial process control systems [patent_app_type] => utility [patent_app_number] => 18/891841 [patent_app_country] => US [patent_app_date] => 2024-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 10303 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18891841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19864749 [patent_doc_number] => 20250103535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => I/O MODULE ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 18/887237 [patent_app_country] => US [patent_app_date] => 2024-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18887237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20587169 [patent_doc_number] => 20260072764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-12 [patent_title] => ARCHIVING PLUG-IN OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 18/882520 [patent_app_country] => US [patent_app_date] => 2024-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18882520 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20570690 [patent_doc_number] => 20260064615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-05 [patent_title] => APPARATUS AND METHODS FOR ESTABLISHING LINK BANDWIDTHS WITHIN DIE INTERCONNECT ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/816339 [patent_app_country] => US [patent_app_date] => 2024-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18816339 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19787398 [patent_doc_number] => 20250061077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => MEMORY EXPANDER, COMPUTING SYSTEMS, AND OPERATING METHOD OF THE HOST DEVICE [patent_app_type] => utility [patent_app_number] => 18/797821 [patent_app_country] => US [patent_app_date] => 2024-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18797821 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19603338 [patent_doc_number] => 20240394218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => SYSTEM AND METHOD FOR OPTIMIZING DATA-TRANSFER AMONG MULTIPLE COMPUTE UNITS IN A DATA-PARALLEL COMPUTING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/794143 [patent_app_country] => US [patent_app_date] => 2024-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18794143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20513368 [patent_doc_number] => 20260037469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-05 [patent_title] => UNIVERSAL INTERFACE FOR CABLE CONNECTORS [patent_app_type] => utility [patent_app_number] => 18/794080 [patent_app_country] => US [patent_app_date] => 2024-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4546 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18794080 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19588283 [patent_doc_number] => 20240385840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => CACHE MANAGEMENT OPERATIONS USING STREAMING ENGINE [patent_app_type] => utility [patent_app_number] => 18/786741 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18786741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19787386 [patent_doc_number] => 20250061065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => CONFIGURING PCI EXPRESS MODULE USING HARDWARE IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 18/781989 [patent_app_country] => US [patent_app_date] => 2024-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18781989 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19558596 [patent_doc_number] => 20240370388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => SYSTEM AND METHOD FOR ENHANCING THROUGHPUT DURING DATA TRANSFER [patent_app_type] => utility [patent_app_number] => 18/778684 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778684 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20273452 [patent_doc_number] => 12443232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Port replicator [patent_app_type] => utility [patent_app_number] => 18/772379 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 5301 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772379 [rel_patent_id] =>[rel_patent_doc_number] =>)