Search

Brian W. Brown

Examiner (ID: 250)

Most Active Art Unit
2101
Art Unit(s)
2899, 2101
Total Applications
731
Issued Applications
680
Pending Applications
0
Abandoned Applications
51

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17364913 [patent_doc_number] => 11231934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => System and method for controlling the order of instruction execution by a target device [patent_app_type] => utility [patent_app_number] => 16/882018 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5409 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882018 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882018
System and method for controlling the order of instruction execution by a target device May 21, 2020 Issued
Array ( [id] => 16271291 [patent_doc_number] => 20200272779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => RECONFIGURABLE INTERCONNECT [patent_app_type] => utility [patent_app_number] => 15/931445 [patent_app_country] => US [patent_app_date] => 2020-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15931445 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/931445
Reconfigurable interconnect May 12, 2020 Issued
Array ( [id] => 16270893 [patent_doc_number] => 20200272380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => COMMUNICATION BETWEEN AN IMAGE FORMING DEVICE AND A REPLACEABLE SUPPLY ITEM [patent_app_type] => utility [patent_app_number] => 16/871780 [patent_app_country] => US [patent_app_date] => 2020-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5794 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16871780 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/871780
COMMUNICATION BETWEEN AN IMAGE FORMING DEVICE AND A REPLACEABLE SUPPLY ITEM May 10, 2020 Abandoned
Array ( [id] => 16439173 [patent_doc_number] => 20200356499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE [patent_app_type] => utility [patent_app_number] => 16/862916 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16862916 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/862916
High capacity memory system with improved command-address and chip-select signaling mode Apr 29, 2020 Issued
Array ( [id] => 16209077 [patent_doc_number] => 20200242067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => System and Method for I/O Aware Processor Configuration [patent_app_type] => utility [patent_app_number] => 16/849678 [patent_app_country] => US [patent_app_date] => 2020-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6615 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16849678 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/849678
System and method for I/O aware processor configuration Apr 14, 2020 Issued
Array ( [id] => 17238432 [patent_doc_number] => 11182312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Memory sub-system manufacturing mode [patent_app_type] => utility [patent_app_number] => 16/838504 [patent_app_country] => US [patent_app_date] => 2020-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6734 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16838504 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/838504
Memory sub-system manufacturing mode Apr 1, 2020 Issued
Array ( [id] => 16844824 [patent_doc_number] => 11016913 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-25 [patent_title] => Inter cluster snoop latency reduction [patent_app_type] => utility [patent_app_number] => 16/834148 [patent_app_country] => US [patent_app_date] => 2020-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16834148 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/834148
Inter cluster snoop latency reduction Mar 29, 2020 Issued
Array ( [id] => 16179112 [patent_doc_number] => 20200226080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => SOLID STATE DRIVE WITH EXTERNAL SOFTWARE EXECUTION TO EFFECT INTERNAL SOLID-STATE DRIVE OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/833422 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6263 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16833422 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/833422
Solid state drive with external software execution to effect internal solid-state drive operations Mar 26, 2020 Issued
Array ( [id] => 17194823 [patent_doc_number] => 11163576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Systems and methods for invisible speculative execution [patent_app_type] => utility [patent_app_number] => 16/825399 [patent_app_country] => US [patent_app_date] => 2020-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 6559 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16825399 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/825399
Systems and methods for invisible speculative execution Mar 19, 2020 Issued
Array ( [id] => 16178983 [patent_doc_number] => 20200225951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => DIGITAL SIGNAL PROCESSING ARRAY USING INTEGRATED PROCESSING ELEMENTS [patent_app_type] => utility [patent_app_number] => 16/823247 [patent_app_country] => US [patent_app_date] => 2020-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10875 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16823247 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/823247
Digital signal processing array using integrated processing elements Mar 17, 2020 Issued
Array ( [id] => 16160609 [patent_doc_number] => 20200218537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => DIGITAL SIGNAL PROCESSING ARRAY USING INTEGRATED PROCESSING ELEMENTS [patent_app_type] => utility [patent_app_number] => 16/823248 [patent_app_country] => US [patent_app_date] => 2020-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16823248 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/823248
DIGITAL SIGNAL PROCESSING ARRAY USING INTEGRATED PROCESSING ELEMENTS Mar 17, 2020 Abandoned
Array ( [id] => 17565122 [patent_doc_number] => 20220129271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => DATA INITIALIZATION TECHNIQUES [patent_app_type] => utility [patent_app_number] => 17/430963 [patent_app_country] => US [patent_app_date] => 2020-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 40729 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17430963 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/430963
Data initialization techniques Mar 13, 2020 Issued
Array ( [id] => 18189780 [patent_doc_number] => 11580371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Method and apparatus to efficiently process and execute Artificial Intelligence operations [patent_app_type] => utility [patent_app_number] => 16/817416 [patent_app_country] => US [patent_app_date] => 2020-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3740 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16817416 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/817416
Method and apparatus to efficiently process and execute Artificial Intelligence operations Mar 11, 2020 Issued
Array ( [id] => 17084064 [patent_doc_number] => 20210279070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => SNAPSHOT TRANSMISSION FROM STORAGE ARRAY TO CLOUD USING MULTI-PATH INPUT-OUTPUT [patent_app_type] => utility [patent_app_number] => 16/811751 [patent_app_country] => US [patent_app_date] => 2020-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16811751 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/811751
Snapshot transmission from storage array to cloud using multi-path input-output Mar 5, 2020 Issued
Array ( [id] => 16240299 [patent_doc_number] => 20200257533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => PROCESSOR AND INSTRUCTION EXECUTION METHOD [patent_app_type] => utility [patent_app_number] => 16/786191 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5674 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16786191 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/786191
Processor and instruction execution method Feb 9, 2020 Issued
Array ( [id] => 16178982 [patent_doc_number] => 20200225950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => MODE-SPECIFIC ENDBRANCH FOR CONTROL FLOW TERMINATION [patent_app_type] => utility [patent_app_number] => 16/741498 [patent_app_country] => US [patent_app_date] => 2020-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741498 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/741498
Mode-specific endbranch for control flow termination Jan 12, 2020 Issued
Array ( [id] => 17528567 [patent_doc_number] => 11301255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Method, apparatus, device, and storage medium for performing processing task [patent_app_type] => utility [patent_app_number] => 16/729989 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6874 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16729989 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/729989
Method, apparatus, device, and storage medium for performing processing task Dec 29, 2019 Issued
Array ( [id] => 16212501 [patent_doc_number] => 20200245491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => HOT-PLUGGABLE CONNECTION FOR DATA COMMUNICATIONS [patent_app_type] => utility [patent_app_number] => 16/726577 [patent_app_country] => US [patent_app_date] => 2019-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10588 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16726577 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/726577
Hot-pluggable connection for data communications Dec 23, 2019 Issued
Array ( [id] => 17252997 [patent_doc_number] => 11188486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Master chip, slave chip, and inter-chip DMA transmission system [patent_app_type] => utility [patent_app_number] => 16/697122 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9751 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16697122 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/697122
Master chip, slave chip, and inter-chip DMA transmission system Nov 25, 2019 Issued
Array ( [id] => 16780121 [patent_doc_number] => 20210117200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => CONTROLLING THE OPERATION OF A DECOUPLED ACCESS-EXECUTE PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/658494 [patent_app_country] => US [patent_app_date] => 2019-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16658494 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/658494
Controlling the operation of a decoupled access-execute processor Oct 20, 2019 Issued
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