Search

Brieanna Tarah Larell Szafran

Examiner (ID: 5269, Phone: (571)270-7627 , Office: P/3765 )

Most Active Art Unit
3765
Art Unit(s)
3765, 3732
Total Applications
513
Issued Applications
144
Pending Applications
3
Abandoned Applications
359

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1260573 [patent_doc_number] => 06668331 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-23 [patent_title] => 'Apparatus and method for successively generating an event to establish a total delay time that is greater than can be expressed by specified data bits in an event memory' [patent_app_type] => B1 [patent_app_number] => 09/535031 [patent_app_country] => US [patent_app_date] => 2000-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 4754 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/668/06668331.pdf [firstpage_image] =>[orig_patent_app_number] => 09535031 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/535031
Apparatus and method for successively generating an event to establish a total delay time that is greater than can be expressed by specified data bits in an event memory Mar 23, 2000 Issued
Array ( [id] => 1100461 [patent_doc_number] => 06823467 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-23 [patent_title] => 'Method and apparatus for arbitrary resolution interval timeouts' [patent_app_type] => B1 [patent_app_number] => 09/512842 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9982 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/823/06823467.pdf [firstpage_image] =>[orig_patent_app_number] => 09512842 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/512842
Method and apparatus for arbitrary resolution interval timeouts Feb 24, 2000 Issued
Array ( [id] => 1218241 [patent_doc_number] => 06711674 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Method of watermarking configuration data in an FPGA by embedding the watermark corresponding to a macro obtained upon encountering a first watermark tag from the macro' [patent_app_type] => B1 [patent_app_number] => 09/513230 [patent_app_country] => US [patent_app_date] => 2000-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3432 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711674.pdf [firstpage_image] =>[orig_patent_app_number] => 09513230 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/513230
Method of watermarking configuration data in an FPGA by embedding the watermark corresponding to a macro obtained upon encountering a first watermark tag from the macro Feb 23, 2000 Issued
Array ( [id] => 1361760 [patent_doc_number] => 06587953 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'System and method for sequential power supply control of prioritized networked printers from the highest priority via a manual switch on of a network printer regardless of its priority' [patent_app_type] => B1 [patent_app_number] => 09/511978 [patent_app_country] => US [patent_app_date] => 2000-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6323 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587953.pdf [firstpage_image] =>[orig_patent_app_number] => 09511978 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/511978
System and method for sequential power supply control of prioritized networked printers from the highest priority via a manual switch on of a network printer regardless of its priority Feb 23, 2000 Issued
Array ( [id] => 1324132 [patent_doc_number] => 06611912 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-26 [patent_title] => 'Method and apparatus having a system BIOS write configuration data of a riser card to a controller configuration space when connecting the riser card to a motherboard' [patent_app_type] => B1 [patent_app_number] => 09/498156 [patent_app_country] => US [patent_app_date] => 2000-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3465 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/611/06611912.pdf [firstpage_image] =>[orig_patent_app_number] => 09498156 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/498156
Method and apparatus having a system BIOS write configuration data of a riser card to a controller configuration space when connecting the riser card to a motherboard Feb 3, 2000 Issued
Array ( [id] => 1218288 [patent_doc_number] => 06711694 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Apparatus and method for generating a modulated clock signal including harmonics that exhibit a known sideband configuration' [patent_app_type] => B1 [patent_app_number] => 09/496739 [patent_app_country] => US [patent_app_date] => 2000-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3942 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711694.pdf [firstpage_image] =>[orig_patent_app_number] => 09496739 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/496739
Apparatus and method for generating a modulated clock signal including harmonics that exhibit a known sideband configuration Feb 2, 2000 Issued
Array ( [id] => 1325539 [patent_doc_number] => 06615360 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Method and system for controlling a power on sequence in response to monitoring respective components of a computer system with multiple CPU sockets to determine proper functionality' [patent_app_type] => B1 [patent_app_number] => 09/491030 [patent_app_country] => US [patent_app_date] => 2000-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4375 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/615/06615360.pdf [firstpage_image] =>[orig_patent_app_number] => 09491030 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/491030
Method and system for controlling a power on sequence in response to monitoring respective components of a computer system with multiple CPU sockets to determine proper functionality Jan 24, 2000 Issued
09/483819 PROMPT RESYNCHRONIZATION FOR A SERIAL INTERFACE Jan 14, 2000 Abandoned
Array ( [id] => 1271993 [patent_doc_number] => 06662303 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Write precompensation circuit and read channel with write precompensation circuit that generates output signals by interpolating between selected phases' [patent_app_type] => B1 [patent_app_number] => 09/480875 [patent_app_country] => US [patent_app_date] => 2000-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2356 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/662/06662303.pdf [firstpage_image] =>[orig_patent_app_number] => 09480875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/480875
Write precompensation circuit and read channel with write precompensation circuit that generates output signals by interpolating between selected phases Jan 9, 2000 Issued
Array ( [id] => 1377646 [patent_doc_number] => 06578156 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Output buffer having a plurality of switching devices being turned on successively at shorter time intervals to achieve increasing drive capability using a predriver' [patent_app_type] => B1 [patent_app_number] => 09/479443 [patent_app_country] => US [patent_app_date] => 2000-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8909 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/578/06578156.pdf [firstpage_image] =>[orig_patent_app_number] => 09479443 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/479443
Output buffer having a plurality of switching devices being turned on successively at shorter time intervals to achieve increasing drive capability using a predriver Jan 6, 2000 Issued
Array ( [id] => 1386331 [patent_doc_number] => 06571345 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Dual-timer process control system' [patent_app_type] => B1 [patent_app_number] => 09/473812 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3163 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571345.pdf [firstpage_image] =>[orig_patent_app_number] => 09473812 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/473812
Dual-timer process control system Dec 27, 1999 Issued
Array ( [id] => 1361732 [patent_doc_number] => 06587951 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Method of powering down a computer system by performing an unconditional shutdown after interrupts of first and second software systems respectively fail following a power button event' [patent_app_type] => B1 [patent_app_number] => 09/471839 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4506 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587951.pdf [firstpage_image] =>[orig_patent_app_number] => 09471839 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/471839
Method of powering down a computer system by performing an unconditional shutdown after interrupts of first and second software systems respectively fail following a power button event Dec 22, 1999 Issued
Array ( [id] => 1324178 [patent_doc_number] => 06611918 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-26 [patent_title] => 'Method and apparatus for changing bias levels to reduce CMOS leakage of a real time clock when switching to a battery mode of operation' [patent_app_type] => B1 [patent_app_number] => 09/469986 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1677 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/611/06611918.pdf [firstpage_image] =>[orig_patent_app_number] => 09469986 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/469986
Method and apparatus for changing bias levels to reduce CMOS leakage of a real time clock when switching to a battery mode of operation Dec 20, 1999 Issued
Array ( [id] => 1401437 [patent_doc_number] => 06564317 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Method and apparatus for securing computer firmware wherein unlocking of nonvolatile memory is prohibited unless address line masking Is disabled during an initialization event' [patent_app_type] => B1 [patent_app_number] => 09/468202 [patent_app_country] => US [patent_app_date] => 1999-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5463 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564317.pdf [firstpage_image] =>[orig_patent_app_number] => 09468202 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/468202
Method and apparatus for securing computer firmware wherein unlocking of nonvolatile memory is prohibited unless address line masking Is disabled during an initialization event Dec 19, 1999 Issued
Array ( [id] => 1289350 [patent_doc_number] => 06647504 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-11 [patent_title] => 'System and method for outputting a sample using a time stamp predicted at a receiving station coupled to an output station via a variable latency bus' [patent_app_type] => B1 [patent_app_number] => 09/451275 [patent_app_country] => US [patent_app_date] => 1999-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2631 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/647/06647504.pdf [firstpage_image] =>[orig_patent_app_number] => 09451275 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/451275
System and method for outputting a sample using a time stamp predicted at a receiving station coupled to an output station via a variable latency bus Nov 29, 1999 Issued
Array ( [id] => 1184833 [patent_doc_number] => 06748525 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-08 [patent_title] => 'Method and apparatus for sending boot programs to workstation computers over a network in a controlled process' [patent_app_type] => B1 [patent_app_number] => 09/451954 [patent_app_country] => US [patent_app_date] => 1999-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7854 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/748/06748525.pdf [firstpage_image] =>[orig_patent_app_number] => 09451954 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/451954
Method and apparatus for sending boot programs to workstation computers over a network in a controlled process Nov 29, 1999 Issued
Array ( [id] => 1250280 [patent_doc_number] => 06675304 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'System for transitioning a processor from a higher to a lower activity state by switching in and out of an impedance on the voltage regulator' [patent_app_type] => B1 [patent_app_number] => 09/450321 [patent_app_country] => US [patent_app_date] => 1999-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2735 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/675/06675304.pdf [firstpage_image] =>[orig_patent_app_number] => 09450321 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/450321
System for transitioning a processor from a higher to a lower activity state by switching in and out of an impedance on the voltage regulator Nov 28, 1999 Issued
Array ( [id] => 1521781 [patent_doc_number] => 06502190 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'System and method for computer system initialization to maximize fault isolation using JTAG' [patent_app_type] => B1 [patent_app_number] => 09/431798 [patent_app_country] => US [patent_app_date] => 1999-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3335 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502190.pdf [firstpage_image] =>[orig_patent_app_number] => 09431798 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/431798
System and method for computer system initialization to maximize fault isolation using JTAG Nov 1, 1999 Issued
Array ( [id] => 1311498 [patent_doc_number] => 06625728 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Method and apparatus for locating and displaying a defective component in a data processing system during a system startup using location and progress codes associated with the component' [patent_app_type] => B1 [patent_app_number] => 09/431797 [patent_app_country] => US [patent_app_date] => 1999-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3062 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625728.pdf [firstpage_image] =>[orig_patent_app_number] => 09431797 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/431797
Method and apparatus for locating and displaying a defective component in a data processing system during a system startup using location and progress codes associated with the component Nov 1, 1999 Issued
Array ( [id] => 1431948 [patent_doc_number] => 06516420 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Data synchronizer using a parallel handshaking pipeline wherein validity indicators generate and send acknowledgement signals to a different clock domain' [patent_app_type] => B1 [patent_app_number] => 09/426265 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4134 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516420.pdf [firstpage_image] =>[orig_patent_app_number] => 09426265 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/426265
Data synchronizer using a parallel handshaking pipeline wherein validity indicators generate and send acknowledgement signals to a different clock domain Oct 24, 1999 Issued
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