| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_title] => 'Apparatus and method for successively generating an event to establish a total delay time that is greater than can be expressed by specified data bits in an event memory'
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[patent_app_number] => 09/535031
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Array
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[patent_doc_number] => 06823467
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[patent_kind] => B1
[patent_issue_date] => 2004-11-23
[patent_title] => 'Method and apparatus for arbitrary resolution interval timeouts'
[patent_app_type] => B1
[patent_app_number] => 09/512842
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/512842 | Method and apparatus for arbitrary resolution interval timeouts | Feb 24, 2000 | Issued |
Array
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[patent_doc_number] => 06711674
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[patent_kind] => B1
[patent_issue_date] => 2004-03-23
[patent_title] => 'Method of watermarking configuration data in an FPGA by embedding the watermark corresponding to a macro obtained upon encountering a first watermark tag from the macro'
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Array
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[patent_doc_number] => 06587953
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[patent_kind] => B1
[patent_issue_date] => 2003-07-01
[patent_title] => 'System and method for sequential power supply control of prioritized networked printers from the highest priority via a manual switch on of a network printer regardless of its priority'
[patent_app_type] => B1
[patent_app_number] => 09/511978
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[patent_issue_date] => 2003-08-26
[patent_title] => 'Method and apparatus having a system BIOS write configuration data of a riser card to a controller configuration space when connecting the riser card to a motherboard'
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[patent_doc_number] => 06711694
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[patent_issue_date] => 2004-03-23
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Array
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[patent_doc_number] => 06615360
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[patent_issue_date] => 2003-09-02
[patent_title] => 'Method and system for controlling a power on sequence in response to monitoring respective components of a computer system with multiple CPU sockets to determine proper functionality'
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[patent_app_number] => 09/491030
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/491030 | Method and system for controlling a power on sequence in response to monitoring respective components of a computer system with multiple CPU sockets to determine proper functionality | Jan 24, 2000 | Issued |
| 09/483819 | PROMPT RESYNCHRONIZATION FOR A SERIAL INTERFACE | Jan 14, 2000 | Abandoned |
Array
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[id] => 1271993
[patent_doc_number] => 06662303
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[patent_issue_date] => 2003-12-09
[patent_title] => 'Write precompensation circuit and read channel with write precompensation circuit that generates output signals by interpolating between selected phases'
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[patent_app_number] => 09/480875
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[patent_issue_date] => 2003-06-10
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[patent_issue_date] => 2003-05-27
[patent_title] => 'Dual-timer process control system'
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Array
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[patent_doc_number] => 06587951
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[patent_issue_date] => 2003-07-01
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