Search

Brieanna Tarah Larell Szafran

Examiner (ID: 5269, Phone: (571)270-7627 , Office: P/3765 )

Most Active Art Unit
3765
Art Unit(s)
3765, 3732
Total Applications
513
Issued Applications
144
Pending Applications
3
Abandoned Applications
359

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1602305 [patent_doc_number] => 06493828 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Information processing apparatus, information processing method, and program storage medium' [patent_app_type] => B1 [patent_app_number] => 09/385398 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4638 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493828.pdf [firstpage_image] =>[orig_patent_app_number] => 09385398 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/385398
Information processing apparatus, information processing method, and program storage medium Aug 29, 1999 Issued
Array ( [id] => 1381925 [patent_doc_number] => 06574728 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Condition code stack architecture systems and methods' [patent_app_type] => B1 [patent_app_number] => 09/371967 [patent_app_country] => US [patent_app_date] => 1999-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3523 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574728.pdf [firstpage_image] =>[orig_patent_app_number] => 09371967 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/371967
Condition code stack architecture systems and methods Aug 9, 1999 Issued
Array ( [id] => 1595973 [patent_doc_number] => 06484256 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Apparatus and method of branch prediction utilizing a comparison of a branch history table to an aliasing table' [patent_app_type] => B1 [patent_app_number] => 09/370680 [patent_app_country] => US [patent_app_date] => 1999-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5060 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/484/06484256.pdf [firstpage_image] =>[orig_patent_app_number] => 09370680 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/370680
Apparatus and method of branch prediction utilizing a comparison of a branch history table to an aliasing table Aug 8, 1999 Issued
Array ( [id] => 7642368 [patent_doc_number] => 06430678 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Scoreboard mechanism for serialized string operations utilizing the XER' [patent_app_type] => B1 [patent_app_number] => 09/363463 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4197 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430678.pdf [firstpage_image] =>[orig_patent_app_number] => 09363463 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/363463
Scoreboard mechanism for serialized string operations utilizing the XER Jul 28, 1999 Issued
Array ( [id] => 1429118 [patent_doc_number] => 06513112 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'System and apparatus for administration of configuration information using a catalog server object to describe and manage requested configuration information to be stored in a table object' [patent_app_type] => B1 [patent_app_number] => 09/360441 [patent_app_country] => US [patent_app_date] => 1999-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9691 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/513/06513112.pdf [firstpage_image] =>[orig_patent_app_number] => 09360441 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/360441
System and apparatus for administration of configuration information using a catalog server object to describe and manage requested configuration information to be stored in a table object Jul 25, 1999 Issued
Array ( [id] => 1485090 [patent_doc_number] => 06453412 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Method and apparatus for reissuing paired MMX instructions singly during exception handling' [patent_app_type] => B1 [patent_app_number] => 09/357703 [patent_app_country] => US [patent_app_date] => 1999-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4033 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453412.pdf [firstpage_image] =>[orig_patent_app_number] => 09357703 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/357703
Method and apparatus for reissuing paired MMX instructions singly during exception handling Jul 19, 1999 Issued
Array ( [id] => 7622352 [patent_doc_number] => 06687814 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Controller with interface attachment' [patent_app_type] => B1 [patent_app_number] => 09/350894 [patent_app_country] => US [patent_app_date] => 1999-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3538 [patent_no_of_claims] => 99 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687814.pdf [firstpage_image] =>[orig_patent_app_number] => 09350894 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/350894
Controller with interface attachment Jul 11, 1999 Issued
Array ( [id] => 1419007 [patent_doc_number] => 06546482 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Invalid configuration detection resource' [patent_app_type] => B1 [patent_app_number] => 09/306871 [patent_app_country] => US [patent_app_date] => 1999-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6067 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546482.pdf [firstpage_image] =>[orig_patent_app_number] => 09306871 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/306871
Invalid configuration detection resource May 6, 1999 Issued
Array ( [id] => 1506049 [patent_doc_number] => 06487671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Elimination of turnaround cycles on multiplexed address/data buses' [patent_app_type] => B1 [patent_app_number] => 09/162600 [patent_app_country] => US [patent_app_date] => 1998-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4743 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487671.pdf [firstpage_image] =>[orig_patent_app_number] => 09162600 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/162600
Elimination of turnaround cycles on multiplexed address/data buses Sep 28, 1998 Issued
Menu