
Brieanna Tarah Larell Szafran
Examiner (ID: 5269, Phone: (571)270-7627 , Office: P/3765 )
| Most Active Art Unit | 3765 |
| Art Unit(s) | 3765, 3732 |
| Total Applications | 513 |
| Issued Applications | 144 |
| Pending Applications | 3 |
| Abandoned Applications | 359 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7140826
[patent_doc_number] => 20050182988
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-18
[patent_title] => 'Adaptive clock skew in a variably loaded memory bus'
[patent_app_type] => utility
[patent_app_number] => 11/107044
[patent_app_country] => US
[patent_app_date] => 2005-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 7063
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[pdf_file] => publications/A1/0182/20050182988.pdf
[firstpage_image] =>[orig_patent_app_number] => 11107044
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/107044 | Adaptive clock skew in a variably loaded memory bus | Apr 14, 2005 | Issued |
Array
(
[id] => 922123
[patent_doc_number] => 07325151
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-01-29
[patent_title] => 'Program, recording medium, method, and information processing apparatus for controlling an execution mode of a CPU'
[patent_app_type] => utility
[patent_app_number] => 11/060474
[patent_app_country] => US
[patent_app_date] => 2005-02-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/325/07325151.pdf
[firstpage_image] =>[orig_patent_app_number] => 11060474
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/060474 | Program, recording medium, method, and information processing apparatus for controlling an execution mode of a CPU | Feb 16, 2005 | Issued |
Array
(
[id] => 860462
[patent_doc_number] => 07376857
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-20
[patent_title] => 'Method of timing calibration using slower data rate pattern'
[patent_app_type] => utility
[patent_app_number] => 11/018384
[patent_app_country] => US
[patent_app_date] => 2004-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[pdf_file] => patents/07/376/07376857.pdf
[firstpage_image] =>[orig_patent_app_number] => 11018384
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/018384 | Method of timing calibration using slower data rate pattern | Dec 21, 2004 | Issued |
Array
(
[id] => 753299
[patent_doc_number] => 07028208
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-04-11
[patent_title] => 'Duty cycle distortion compensation for the data output of a memory device'
[patent_app_type] => utility
[patent_app_number] => 11/018810
[patent_app_country] => US
[patent_app_date] => 2004-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 6230
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/028/07028208.pdf
[firstpage_image] =>[orig_patent_app_number] => 11018810
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/018810 | Duty cycle distortion compensation for the data output of a memory device | Dec 20, 2004 | Issued |
Array
(
[id] => 7100166
[patent_doc_number] => 20050132080
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-16
[patent_title] => 'Coordinating protocol for a multi-processor system'
[patent_app_type] => utility
[patent_app_number] => 10/961516
[patent_app_country] => US
[patent_app_date] => 2004-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3105
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[pdf_file] => publications/A1/0132/20050132080.pdf
[firstpage_image] =>[orig_patent_app_number] => 10961516
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/961516 | Coordinating protocol for a multi-processor system | Oct 7, 2004 | Abandoned |
Array
(
[id] => 5722121
[patent_doc_number] => 20060074897
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-06
[patent_title] => 'System and method for dynamic data masking'
[patent_app_type] => utility
[patent_app_number] => 10/957971
[patent_app_country] => US
[patent_app_date] => 2004-10-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0074/20060074897.pdf
[firstpage_image] =>[orig_patent_app_number] => 10957971
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/957971 | System and method for dynamic data masking | Oct 3, 2004 | Abandoned |
Array
(
[id] => 427870
[patent_doc_number] => 07272743
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-18
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 10/934462
[patent_app_country] => US
[patent_app_date] => 2004-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/272/07272743.pdf
[firstpage_image] =>[orig_patent_app_number] => 10934462
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/934462 | Semiconductor integrated circuit | Sep 6, 2004 | Issued |
Array
(
[id] => 7013370
[patent_doc_number] => 20050066077
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-24
[patent_title] => 'Data transfer control device and electronic instrument'
[patent_app_type] => utility
[patent_app_number] => 10/934461
[patent_app_country] => US
[patent_app_date] => 2004-09-07
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[pdf_file] => publications/A1/0066/20050066077.pdf
[firstpage_image] =>[orig_patent_app_number] => 10934461
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/934461 | Data transfer control device and electronic instrument | Sep 6, 2004 | Issued |
Array
(
[id] => 7120255
[patent_doc_number] => 20050012084
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-20
[patent_title] => 'Portable fencing system and components therefor'
[patent_app_type] => utility
[patent_app_number] => 10/914900
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[patent_drawing_sheets_cnt] => 9
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[pdf_file] => publications/A1/0012/20050012084.pdf
[firstpage_image] =>[orig_patent_app_number] => 10914900
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/914900 | Portable fencing system and components therefor | Aug 9, 2004 | Issued |
Array
(
[id] => 434983
[patent_doc_number] => 07266680
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-09-04
[patent_title] => 'Method and apparatus for loading configuration data'
[patent_app_type] => utility
[patent_app_number] => 10/901689
[patent_app_country] => US
[patent_app_date] => 2004-07-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/266/07266680.pdf
[firstpage_image] =>[orig_patent_app_number] => 10901689
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/901689 | Method and apparatus for loading configuration data | Jul 28, 2004 | Issued |
Array
(
[id] => 451238
[patent_doc_number] => 07254732
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-07
[patent_title] => 'Method and apparatus of automatic power management control for serial ATA device directly attached to SAS/SATA host controller'
[patent_app_type] => utility
[patent_app_number] => 10/901518
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[pdf_file] => patents/07/254/07254732.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/901518 | Method and apparatus of automatic power management control for serial ATA device directly attached to SAS/SATA host controller | Jul 28, 2004 | Issued |
Array
(
[id] => 7449779
[patent_doc_number] => 20040268169
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[patent_issue_date] => 2004-12-30
[patent_title] => 'Method and apparatus of automatic power management control for native command queuing Serial ATA device'
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Array
(
[id] => 7091986
[patent_doc_number] => 20050010831
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[patent_title] => 'Method and apparatus of automatic power management control for Serial ATA interface utilizing a combination of IOP control and specialized hardware control'
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Array
(
[id] => 444441
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[patent_title] => 'Power regulation system and method for a portable electronic device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/900770 | Power regulation system and method for a portable electronic device | Jul 27, 2004 | Issued |
Array
(
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[patent_title] => 'Method and apparatus for processing data in a reconfigurable manner'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/892537 | Method and apparatus for processing data in a reconfigurable manner | Jul 13, 2004 | Abandoned |
Array
(
[id] => 518571
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[patent_title] => 'Apparatus and method for initializing coprocessor for use in system comprised of main processor and coprocessor'
[patent_app_type] => utility
[patent_app_number] => 10/864459
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/864459 | Apparatus and method for initializing coprocessor for use in system comprised of main processor and coprocessor | Jun 9, 2004 | Issued |
Array
(
[id] => 7601911
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[patent_issue_date] => 2007-06-26
[patent_title] => 'Power supply control circuit for memories, method thereof and apparatus equipped with memories'
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/863425 | Bootstrap method and apparatus with plural interchangeable boot code images | Jun 7, 2004 | Abandoned |
Array
(
[id] => 485777
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[patent_title] => 'Maintenance terminal of disk array device'
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[firstpage_image] =>[orig_patent_app_number] => 10849120
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/849120 | Maintenance terminal of disk array device | May 19, 2004 | Issued |