Search

Brigitte A. Paterson

Examiner (ID: 17368, Phone: (571)272-1752 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812, 2896
Total Applications
448
Issued Applications
314
Pending Applications
62
Abandoned Applications
94

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10823683 [patent_doc_number] => 20160169848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'DATA PROCESSING DEVICE FOR CHROMATOGRAPH AND DATA PROCESSING METHOD FOR CHROMATOGRAPH' [patent_app_type] => utility [patent_app_number] => 14/902638 [patent_app_country] => US [patent_app_date] => 2013-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4262 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14902638 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/902638
Data processing device for chromatograph and data processing method for chromatograph Aug 4, 2013 Issued
Array ( [id] => 9269220 [patent_doc_number] => 20140024138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-23 [patent_title] => 'METHOD FOR ETCHING METAL LAYER AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/941071 [patent_app_country] => US [patent_app_date] => 2013-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6463 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13941071 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/941071
METHOD FOR ETCHING METAL LAYER AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME Jul 11, 2013 Abandoned
Array ( [id] => 10099869 [patent_doc_number] => 09136187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Method of adjusting a threshold voltage of a transistor in the forming of a semiconductor device including the transistor' [patent_app_type] => utility [patent_app_number] => 13/940545 [patent_app_country] => US [patent_app_date] => 2013-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13940545 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/940545
Method of adjusting a threshold voltage of a transistor in the forming of a semiconductor device including the transistor Jul 11, 2013 Issued
Array ( [id] => 10870200 [patent_doc_number] => 08895396 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-11-25 [patent_title] => 'Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures' [patent_app_type] => utility [patent_app_number] => 13/940220 [patent_app_country] => US [patent_app_date] => 2013-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3989 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13940220 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/940220
Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures Jul 10, 2013 Issued
Array ( [id] => 10016164 [patent_doc_number] => 09059185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-16 [patent_title] => 'Copper leadframe finish for copper wire bonding' [patent_app_type] => utility [patent_app_number] => 13/939328 [patent_app_country] => US [patent_app_date] => 2013-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 4128 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13939328 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/939328
Copper leadframe finish for copper wire bonding Jul 10, 2013 Issued
Array ( [id] => 9805832 [patent_doc_number] => 20150017777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-15 [patent_title] => 'METHOD OF FABRICATING MOS DEVICE' [patent_app_type] => utility [patent_app_number] => 13/940103 [patent_app_country] => US [patent_app_date] => 2013-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3264 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13940103 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/940103
Method of fabricating a MOS device using a stress-generating material Jul 10, 2013 Issued
Array ( [id] => 12355863 [patent_doc_number] => 09954135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Solar cell manufacturing method [patent_app_type] => utility [patent_app_number] => 14/901778 [patent_app_country] => US [patent_app_date] => 2013-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3266 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14901778 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/901778
Solar cell manufacturing method Jul 10, 2013 Issued
Array ( [id] => 9802759 [patent_doc_number] => 20150014704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-15 [patent_title] => 'Bipolar Transistor and a Method for Manufacturing a Bipolar Transistor' [patent_app_type] => utility [patent_app_number] => 13/939358 [patent_app_country] => US [patent_app_date] => 2013-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7579 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13939358 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/939358
Bipolar transistor and a method for manufacturing a bipolar transistor Jul 10, 2013 Issued
Array ( [id] => 9802826 [patent_doc_number] => 20150014771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-15 [patent_title] => 'DUAL L-SHAPED DRIFT REGIONS IN AN LDMOS DEVICE AND METHOD OF MAKING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/939353 [patent_app_country] => US [patent_app_date] => 2013-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13939353 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/939353
Dual L-shaped drift regions in an LDMOS device and method of making the same Jul 10, 2013 Issued
Array ( [id] => 10463758 [patent_doc_number] => 20150348773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'ALUMINUM-NITRIDE BUFFER AND ACTIVE LAYERS BY PHYSICAL VAPOR DEPOSITION' [patent_app_type] => utility [patent_app_number] => 14/410790 [patent_app_country] => US [patent_app_date] => 2013-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14931 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14410790 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/410790
Aluminum-nitride buffer and active layers by physical vapor deposition Jun 30, 2013 Issued
Array ( [id] => 10219964 [patent_doc_number] => 20150104957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-16 [patent_title] => 'RESIST MASK PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 14/403794 [patent_app_country] => US [patent_app_date] => 2013-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7506 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14403794 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/403794
Resist mask processing method using hydrogen containing plasma Jun 16, 2013 Issued
Array ( [id] => 10544780 [patent_doc_number] => 09269919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-23 [patent_title] => 'Stacked organic light emitting diode' [patent_app_type] => utility [patent_app_number] => 14/396932 [patent_app_country] => US [patent_app_date] => 2013-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 15552 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14396932 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/396932
Stacked organic light emitting diode May 30, 2013 Issued
Array ( [id] => 9034370 [patent_doc_number] => 20130237008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-12 [patent_title] => 'METHOD FOR MANUFACTURING NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/870424 [patent_app_country] => US [patent_app_date] => 2013-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9402 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13870424 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/870424
METHOD FOR MANUFACTURING NONVOLATILE MEMORY DEVICE Apr 24, 2013 Abandoned
Array ( [id] => 10199072 [patent_doc_number] => 20150084058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'LIGHT EMITTING DEVICE GROWN ON A SILICON SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/384173 [patent_app_country] => US [patent_app_date] => 2013-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3906 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14384173 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/384173
LIGHT EMITTING DEVICE GROWN ON A SILICON SUBSTRATE Mar 17, 2013 Abandoned
Array ( [id] => 9875138 [patent_doc_number] => 08962405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Method of manufacturing semiconductor device by mounting and positioning a semiconductor die using detection marks' [patent_app_type] => utility [patent_app_number] => 13/798589 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7467 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13798589 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/798589
Method of manufacturing semiconductor device by mounting and positioning a semiconductor die using detection marks Mar 12, 2013 Issued
Array ( [id] => 9937306 [patent_doc_number] => 08987111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Method of manufacturing a three dimensional array having buried word lines of different heights and widths' [patent_app_type] => utility [patent_app_number] => 13/789930 [patent_app_country] => US [patent_app_date] => 2013-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 7441 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13789930 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/789930
Method of manufacturing a three dimensional array having buried word lines of different heights and widths Mar 7, 2013 Issued
Array ( [id] => 9817586 [patent_doc_number] => 08927369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-06 [patent_title] => 'Method of forming a trench gate MOSFET having a thick bottom oxide' [patent_app_type] => utility [patent_app_number] => 13/789692 [patent_app_country] => US [patent_app_date] => 2013-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4060 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13789692 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/789692
Method of forming a trench gate MOSFET having a thick bottom oxide Mar 7, 2013 Issued
Array ( [id] => 9720363 [patent_doc_number] => 20140256064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'METHODS OF REPAIRING DAMAGED INSULATING MATERIALS BY INTRODUCING CARBON INTO THE LAYER OF INSULATING MATERIAL' [patent_app_type] => utility [patent_app_number] => 13/789966 [patent_app_country] => US [patent_app_date] => 2013-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5659 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13789966 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/789966
METHODS OF REPAIRING DAMAGED INSULATING MATERIALS BY INTRODUCING CARBON INTO THE LAYER OF INSULATING MATERIAL Mar 7, 2013 Abandoned
Array ( [id] => 12256868 [patent_doc_number] => 09929017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-27 [patent_title] => 'Etching method using hydrogen peroxide solution containing tungsten' [patent_app_type] => utility [patent_app_number] => 13/788216 [patent_app_country] => US [patent_app_date] => 2013-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4014 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13788216 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/788216
Etching method using hydrogen peroxide solution containing tungsten Mar 6, 2013 Issued
Array ( [id] => 9034350 [patent_doc_number] => 20130236988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-12 [patent_title] => 'METHODS AND STRUCTURES OF INTEGRATED MEMS-CMOS DEVICES' [patent_app_type] => utility [patent_app_number] => 13/788503 [patent_app_country] => US [patent_app_date] => 2013-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 9745 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13788503 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/788503
Methods and structures of integrated MEMS-CMOS devices Mar 6, 2013 Issued
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