Brigitte A. Paterson

Array ( [id] => 10645361 [patent_doc_number] => 09362236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'Package structures and methods for forming the same' [patent_app_type] => utility [patent_app_number] => 13/788135 [patent_app_country] => US [patent_app_date] => 2013-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3948 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13788135 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10876118 [patent_doc_number] => 08900903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-02 [patent_title] => 'Method for producing optical semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/787883 [patent_app_country] => US [patent_app_date] => 2013-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 28 [patent_no_of_words] => 11901 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 461 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13787883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9054642 [patent_doc_number] => 20130252356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'SUPPORTING SUBSTRATE, METHOD FOR FABRICATING SEMICONDUCTOR DEVICE, AND METHOD FOR INSPECTING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/789517 [patent_app_country] => US [patent_app_date] => 2013-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3729 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13789517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10066770 [patent_doc_number] => 09105629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-11 [patent_title] => 'Selective area heating for 3D chip stack' [patent_app_type] => utility [patent_app_number] => 13/787913 [patent_app_country] => US [patent_app_date] => 2013-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5815 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13787913 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9174550 [patent_doc_number] => 20130316535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'METHODS OF FORMING SEMICONDUCTOR DEVICES WITH METAL SILICIDE USING PRE-AMORPHIZATION IMPLANTS AND DEVICES SO FORMED' [patent_app_type] => utility [patent_app_number] => 13/788599 [patent_app_country] => US [patent_app_date] => 2013-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7021 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13788599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9031597 [patent_doc_number] => 20130234235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-12 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/788295 [patent_app_country] => US [patent_app_date] => 2013-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7598 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13788295 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9153500 [patent_doc_number] => 08586406 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-11-19 [patent_title] => 'Method for forming an oxide thin film transistor' [patent_app_type] => utility [patent_app_number] => 13/789641 [patent_app_country] => US [patent_app_date] => 2013-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3372 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13789641 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10610989 [patent_doc_number] => 09331032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'Hybrid bonding and apparatus for performing the same' [patent_app_type] => utility [patent_app_number] => 13/787566 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3788 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13787566 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9676760 [patent_doc_number] => 08815669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Metal gate structures for CMOS transistor devices having reduced parasitic capacitance' [patent_app_type] => utility [patent_app_number] => 13/775436 [patent_app_country] => US [patent_app_date] => 2013-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 36 [patent_no_of_words] => 4392 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13775436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9375675 [patent_doc_number] => 08679939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-25 [patent_title] => 'Manufacturable high-k DRAM MIM capacitor structure' [patent_app_type] => utility [patent_app_number] => 13/737467 [patent_app_country] => US [patent_app_date] => 2013-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13737467 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9140855 [patent_doc_number] => 08581318 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-11-12 [patent_title] => 'Enhanced non-noble electrode layers for DRAM capacitor cell' [patent_app_type] => utility [patent_app_number] => 13/737209 [patent_app_country] => US [patent_app_date] => 2013-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 14718 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13737209 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9977423 [patent_doc_number] => 09023735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-05 [patent_title] => 'Etchant composition and manufacturing method for thin film transistor using the same' [patent_app_type] => utility [patent_app_number] => 13/728348 [patent_app_country] => US [patent_app_date] => 2012-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 6592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13728348 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10028910 [patent_doc_number] => 09070823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-30 [patent_title] => 'Method for making a light emitting diode having three dimensional nano-structures' [patent_app_type] => utility [patent_app_number] => 13/728043 [patent_app_country] => US [patent_app_date] => 2012-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6163 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13728043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8891759 [patent_doc_number] => 20130164943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'Substrate Processing Apparatus and Method of Manufacturing Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 13/727193 [patent_app_country] => US [patent_app_date] => 2012-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9679 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13727193 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8891761 [patent_doc_number] => 20130164945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'FILM DEPOSITION METHOD' [patent_app_type] => utility [patent_app_number] => 13/726724 [patent_app_country] => US [patent_app_date] => 2012-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10061 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13726724 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9561386 [patent_doc_number] => 20140179099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'METHODS AND STRUCTURE FOR CARRIER-LESS THIN WAFER HANDLING' [patent_app_type] => utility [patent_app_number] => 13/724223 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7482 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13724223 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9557890 [patent_doc_number] => 20140175603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'Method of Forming an Asymmetric MIMCAP or a Schottky Device as a Selector Element for a Cross-Bar Memory Array' [patent_app_type] => utility [patent_app_number] => 13/722885 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13722885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10073581 [patent_doc_number] => 09111946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-18 [patent_title] => 'Method of thinning a wafer to provide a raised peripheral edge' [patent_app_type] => utility [patent_app_number] => 13/722340 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 6804 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13722340 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9561380 [patent_doc_number] => 20140179093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'GATE STRUCTURE FORMATION PROCESSES' [patent_app_type] => utility [patent_app_number] => 13/721132 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3732 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13721132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9184287 [patent_doc_number] => 08624223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Side-gate defined tunable nanoconstriction in double-gated graphene multilayers' [patent_app_type] => utility [patent_app_number] => 13/668401 [patent_app_country] => US [patent_app_date] => 2012-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 4574 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13668401 [rel_patent_id] =>[rel_patent_doc_number] =>)