
Brigitte A. Paterson
Examiner (ID: 17368, Phone: (571)272-1752 , Office: P/2812 )
| Most Active Art Unit | 2812 |
| Art Unit(s) | 2812, 2896 |
| Total Applications | 448 |
| Issued Applications | 314 |
| Pending Applications | 62 |
| Abandoned Applications | 94 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9134997
[patent_doc_number] => 20130295712
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-11-07
[patent_title] => 'METHODS OF TEXTURING SURFACES FOR CONTROLLED REFLECTION'
[patent_app_type] => utility
[patent_app_number] => 13/463448
[patent_app_country] => US
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13463448
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Array
(
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[patent_doc_number] => 20120282751
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[patent_issue_date] => 2012-11-08
[patent_title] => 'METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING FINE PATTERNS'
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Array
(
[id] => 9131920
[patent_doc_number] => 20130292633
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[patent_kind] => A1
[patent_issue_date] => 2013-11-07
[patent_title] => 'ETCH BIAS HOMOGENIZATION'
[patent_app_type] => utility
[patent_app_number] => 13/463245
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Array
(
[id] => 9135006
[patent_doc_number] => 20130295720
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-11-07
[patent_title] => 'METHODS FOR MANUFACTURING A CHIP PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 13/461859
[patent_app_country] => US
[patent_app_date] => 2012-05-02
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Array
(
[id] => 8489621
[patent_doc_number] => 20120289028
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[patent_issue_date] => 2012-11-15
[patent_title] => 'WAFER DIVIDING METHOD'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/462229 | Wafer dividing method | May 1, 2012 | Issued |
Array
(
[id] => 11645296
[patent_doc_number] => 09666690
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[patent_kind] => B2
[patent_issue_date] => 2017-05-30
[patent_title] => 'Integrated circuit and method for fabricating the same having a replacement gate structure'
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Array
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[patent_doc_number] => 20130295699
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[patent_title] => 'METHOD FOR TESTING THROUGH-SILICON-VIA (TSV) STRUCTURES'
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Array
(
[id] => 9135052
[patent_doc_number] => 20130295767
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[patent_title] => 'INCREASED TRANSISTOR PERFORMANCE BY IMPLEMENTING AN ADDITIONAL CLEANING PROCESS IN A STRESS LINER APPROACH'
[patent_app_type] => utility
[patent_app_number] => 13/462246
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/462246 | INCREASED TRANSISTOR PERFORMANCE BY IMPLEMENTING AN ADDITIONAL CLEANING PROCESS IN A STRESS LINER APPROACH | May 1, 2012 | Abandoned |
Array
(
[id] => 8963631
[patent_doc_number] => 20130203233
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[patent_issue_date] => 2013-08-08
[patent_title] => 'MANUFACTURING METHOD OF MEMORY CAPACITOR WITHOUT MOAT STRUCTURE'
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Array
(
[id] => 10882354
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[patent_kind] => B2
[patent_issue_date] => 2014-12-09
[patent_title] => 'Patterning slit sheet assembly, organic layer deposition apparatus, method of manufacturing organic light-emitting display apparatus, and the organic light-emitting display apparatus'
[patent_app_type] => utility
[patent_app_number] => 13/461669
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/461669 | Patterning slit sheet assembly, organic layer deposition apparatus, method of manufacturing organic light-emitting display apparatus, and the organic light-emitting display apparatus | Apr 30, 2012 | Issued |
Array
(
[id] => 9135033
[patent_doc_number] => 20130295748
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[patent_issue_date] => 2013-11-07
[patent_title] => 'METHOD OF UNIFORM SELENIZATION AND SULFERIZATION IN A TUBE FURNACE'
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Array
(
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Array
(
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Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/359548 | Method of separating semiconductor die using material modification | Jan 26, 2012 | Issued |
Array
(
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/359385 | Process for depositing electrode with high effective work function | Jan 25, 2012 | Issued |