
Britt D. Hanley
Examiner (ID: 382, Phone: (571)270-3042 , Office: P/2875 )
| Most Active Art Unit | 2875 |
| Art Unit(s) | 2893, 2875, 2809, 2821, 2889, 2879 |
| Total Applications | 956 |
| Issued Applications | 682 |
| Pending Applications | 22 |
| Abandoned Applications | 261 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4956057
[patent_doc_number] => 20080189081
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-07
[patent_title] => 'SYSTEM AND METHOD FOR ANALYZING GEOMETRIC DEVIATIONS OF A PHYSICAL OBJECT'
[patent_app_type] => utility
[patent_app_number] => 11/859793
[patent_app_country] => US
[patent_app_date] => 2007-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3125
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0189/20080189081.pdf
[firstpage_image] =>[orig_patent_app_number] => 11859793
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/859793 | SYSTEM AND METHOD FOR ANALYZING GEOMETRIC DEVIATIONS OF A PHYSICAL OBJECT | Sep 23, 2007 | Abandoned |
Array
(
[id] => 5459545
[patent_doc_number] => 20090259697
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-15
[patent_title] => 'DATABASE SYNCHRONIZATION SYSTEM AND DATABASE SYNCHRONIZATION METHOD'
[patent_app_type] => utility
[patent_app_number] => 12/439200
[patent_app_country] => US
[patent_app_date] => 2007-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6917
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0259/20090259697.pdf
[firstpage_image] =>[orig_patent_app_number] => 12439200
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/439200 | DATABASE SYNCHRONIZATION SYSTEM AND DATABASE SYNCHRONIZATION METHOD | Aug 23, 2007 | Abandoned |
Array
(
[id] => 5417670
[patent_doc_number] => 20090043557
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-12
[patent_title] => 'Method, System, and Apparatus for Emulating Functionality of a Network Appliance in a Logically Partitioned Environment'
[patent_app_type] => utility
[patent_app_number] => 11/835486
[patent_app_country] => US
[patent_app_date] => 2007-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2877
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0043/20090043557.pdf
[firstpage_image] =>[orig_patent_app_number] => 11835486
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/835486 | Method, System, and Apparatus for Emulating Functionality of a Network Appliance in a Logically Partitioned Environment | Aug 7, 2007 | Abandoned |
Array
(
[id] => 5522679
[patent_doc_number] => 20090030660
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-29
[patent_title] => 'METHOD AND APPARATUS FOR GENERATING FULLY DETAILED THREE-DIMENSIONAL ELECTRONIC PACKAGE AND PCB BOARD MODELS'
[patent_app_type] => utility
[patent_app_number] => 11/782393
[patent_app_country] => US
[patent_app_date] => 2007-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4064
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0030/20090030660.pdf
[firstpage_image] =>[orig_patent_app_number] => 11782393
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/782393 | METHOD AND APPARATUS FOR GENERATING FULLY DETAILED THREE-DIMENSIONAL ELECTRONIC PACKAGE AND PCB BOARD MODELS | Jul 23, 2007 | Abandoned |
Array
(
[id] => 5291647
[patent_doc_number] => 20090024377
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-22
[patent_title] => 'System and Method for Modeling Semiconductor Devices Using Pre-Processing'
[patent_app_type] => utility
[patent_app_number] => 11/778454
[patent_app_country] => US
[patent_app_date] => 2007-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2468
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0024/20090024377.pdf
[firstpage_image] =>[orig_patent_app_number] => 11778454
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/778454 | System and Method for Modeling Semiconductor Devices Using Pre-Processing | Jul 15, 2007 | Abandoned |
Array
(
[id] => 4862801
[patent_doc_number] => 20080271019
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-30
[patent_title] => 'System and Method for Creating a Virtual Assurance System'
[patent_app_type] => utility
[patent_app_number] => 11/772679
[patent_app_country] => US
[patent_app_date] => 2007-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 12054
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0271/20080271019.pdf
[firstpage_image] =>[orig_patent_app_number] => 11772679
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/772679 | System and Method for Creating a Virtual Assurance System | Jul 1, 2007 | Abandoned |
Array
(
[id] => 4862800
[patent_doc_number] => 20080271018
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-30
[patent_title] => 'System and Method for Managing an Assurance System'
[patent_app_type] => utility
[patent_app_number] => 11/772673
[patent_app_country] => US
[patent_app_date] => 2007-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 11395
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0271/20080271018.pdf
[firstpage_image] =>[orig_patent_app_number] => 11772673
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/772673 | System and Method for Managing an Assurance System | Jul 1, 2007 | Abandoned |
Array
(
[id] => 4861254
[patent_doc_number] => 20080270104
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-30
[patent_title] => 'System and Method for Creating an Assurance System in a Mixed Environment'
[patent_app_type] => utility
[patent_app_number] => 11/772667
[patent_app_country] => US
[patent_app_date] => 2007-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 11907
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0270/20080270104.pdf
[firstpage_image] =>[orig_patent_app_number] => 11772667
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/772667 | System and Method for Creating an Assurance System in a Mixed Environment | Jul 1, 2007 | Abandoned |
Array
(
[id] => 5350705
[patent_doc_number] => 20090006066
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-01
[patent_title] => 'Method and System for Automatic Selection of Test Cases'
[patent_app_type] => utility
[patent_app_number] => 11/769794
[patent_app_country] => US
[patent_app_date] => 2007-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4992
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0006/20090006066.pdf
[firstpage_image] =>[orig_patent_app_number] => 11769794
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/769794 | Method and System for Automatic Selection of Test Cases | Jun 27, 2007 | Abandoned |
Array
(
[id] => 4900455
[patent_doc_number] => 20080120069
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-22
[patent_title] => 'GENERATING AN ANALYTICAL MODEL OF BUILDING FOR USE IN THERMAL MODELING AND ENVIRONMENTAL ANALYSES'
[patent_app_type] => utility
[patent_app_number] => 11/740534
[patent_app_country] => US
[patent_app_date] => 2007-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4528
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0120/20080120069.pdf
[firstpage_image] =>[orig_patent_app_number] => 11740534
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/740534 | GENERATING AN ANALYTICAL MODEL OF BUILDING FOR USE IN THERMAL MODELING AND ENVIRONMENTAL ANALYSES | Apr 25, 2007 | Abandoned |
Array
(
[id] => 4862645
[patent_doc_number] => 20080270959
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-30
[patent_title] => 'Influencing functional simulation of a system by timing simulation of the system'
[patent_app_type] => utility
[patent_app_number] => 11/740254
[patent_app_country] => US
[patent_app_date] => 2007-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3854
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0270/20080270959.pdf
[firstpage_image] =>[orig_patent_app_number] => 11740254
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/740254 | Influencing functional simulation of a system by timing simulation of the system | Apr 24, 2007 | Abandoned |
Array
(
[id] => 4652824
[patent_doc_number] => 20080040081
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-14
[patent_title] => 'SIMULATION METHOD FOR IMPROVING FREEDOM OF SETTING PARAMETERS RELATING TO INPUT/OUTPUT CHARACTERISTICS OF A MEMORY CHIP'
[patent_app_type] => utility
[patent_app_number] => 11/676183
[patent_app_country] => US
[patent_app_date] => 2007-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6362
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0040/20080040081.pdf
[firstpage_image] =>[orig_patent_app_number] => 11676183
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/676183 | SIMULATION METHOD FOR IMPROVING FREEDOM OF SETTING PARAMETERS RELATING TO INPUT/OUTPUT CHARACTERISTICS OF A MEMORY CHIP | Feb 15, 2007 | Abandoned |
Array
(
[id] => 4900454
[patent_doc_number] => 20080120068
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-22
[patent_title] => 'GENERATING AN ANALYTICAL MODEL OF A BUILDING FOR USE IN THERMAL MODELING AND ENVIRONMENTAL ANALYSES'
[patent_app_type] => utility
[patent_app_number] => 11/670260
[patent_app_country] => US
[patent_app_date] => 2007-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4528
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0120/20080120068.pdf
[firstpage_image] =>[orig_patent_app_number] => 11670260
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/670260 | GENERATING AN ANALYTICAL MODEL OF A BUILDING FOR USE IN THERMAL MODELING AND ENVIRONMENTAL ANALYSES | Jan 31, 2007 | Abandoned |
Array
(
[id] => 4847035
[patent_doc_number] => 20080183443
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-31
[patent_title] => 'STATISTICAL SIMULATION OF ON CHIP INTERCONNECTS'
[patent_app_type] => utility
[patent_app_number] => 11/669173
[patent_app_country] => US
[patent_app_date] => 2007-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4112
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0183/20080183443.pdf
[firstpage_image] =>[orig_patent_app_number] => 11669173
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/669173 | STATISTICAL SIMULATION OF ON CHIP INTERCONNECTS | Jan 30, 2007 | Abandoned |
Array
(
[id] => 4527769
[patent_doc_number] => 07912694
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-22
[patent_title] => 'Print events in the simulation of a digital system'
[patent_app_type] => utility
[patent_app_number] => 11/668542
[patent_app_country] => US
[patent_app_date] => 2007-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 23
[patent_no_of_words] => 17794
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 367
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/912/07912694.pdf
[firstpage_image] =>[orig_patent_app_number] => 11668542
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/668542 | Print events in the simulation of a digital system | Jan 29, 2007 | Issued |
| 11/627972 | High resolution Fourier analysis of signals produced by circuit simulators | Jan 27, 2007 | Abandoned |
Array
(
[id] => 4766306
[patent_doc_number] => 20080177518
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-24
[patent_title] => 'Integrated Microfluidic System Design Using Mixed Methodology Simulations'
[patent_app_type] => utility
[patent_app_number] => 11/624589
[patent_app_country] => US
[patent_app_date] => 2007-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 12518
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0177/20080177518.pdf
[firstpage_image] =>[orig_patent_app_number] => 11624589
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/624589 | Integrated Microfluidic System Design Using Mixed Methodology Simulations | Jan 17, 2007 | Abandoned |
Array
(
[id] => 4928480
[patent_doc_number] => 20080167843
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-10
[patent_title] => 'One pass modeling of data sets'
[patent_app_type] => utility
[patent_app_number] => 11/650891
[patent_app_country] => US
[patent_app_date] => 2007-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2971
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0167/20080167843.pdf
[firstpage_image] =>[orig_patent_app_number] => 11650891
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/650891 | One pass modeling of data sets | Jan 7, 2007 | Abandoned |
Array
(
[id] => 4658829
[patent_doc_number] => 20080027691
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-31
[patent_title] => 'Device manufacturing support apparatus, simulation method for device manufacturing support apparatus, and device manufacturing apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/607995
[patent_app_country] => US
[patent_app_date] => 2006-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3994
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0027/20080027691.pdf
[firstpage_image] =>[orig_patent_app_number] => 11607995
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/607995 | Device manufacturing support apparatus, simulation method for device manufacturing support apparatus, and device manufacturing apparatus | Dec 3, 2006 | Abandoned |
Array
(
[id] => 5127665
[patent_doc_number] => 20070239936
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-11
[patent_title] => 'Method and apparatus for statistically modeling a processor in a computer system'
[patent_app_type] => utility
[patent_app_number] => 11/601030
[patent_app_country] => US
[patent_app_date] => 2006-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7286
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0239/20070239936.pdf
[firstpage_image] =>[orig_patent_app_number] => 11601030
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/601030 | Method and apparatus for statistically modeling a processor in a computer system | Nov 16, 2006 | Abandoned |