Search

Brittany Renee Peko

Examiner (ID: 9934)

Most Active Art Unit
3661
Art Unit(s)
3661
Total Applications
134
Issued Applications
81
Pending Applications
37
Abandoned Applications
16

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14542505 [patent_doc_number] => 20190206874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/294934 [patent_app_country] => US [patent_app_date] => 2019-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4886 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16294934 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/294934
Semiconductor memory device Mar 6, 2019 Issued
Array ( [id] => 14509691 [patent_doc_number] => 20190198500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => FORMATION OF FULL METAL GATE TO SUPPRESS INTERFICIAL LAYER GROWTH [patent_app_type] => utility [patent_app_number] => 16/293853 [patent_app_country] => US [patent_app_date] => 2019-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16293853 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/293853
FORMATION OF FULL METAL GATE TO SUPPRESS INTERFICIAL LAYER GROWTH Mar 5, 2019 Abandoned
Array ( [id] => 17818621 [patent_doc_number] => 11424245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Self-aligned gate endcap (SAGE) architecture having gate contacts [patent_app_type] => utility [patent_app_number] => 16/294210 [patent_app_country] => US [patent_app_date] => 2019-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 11871 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16294210 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/294210
Self-aligned gate endcap (SAGE) architecture having gate contacts Mar 5, 2019 Issued
Array ( [id] => 16356436 [patent_doc_number] => 10796954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Semiconductor structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 16/281689 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6687 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281689 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/281689
Semiconductor structure and method for forming the same Feb 20, 2019 Issued
Array ( [id] => 16119747 [patent_doc_number] => 20200211896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => SEMICONDUCTOR SUBSTRATE AND METHOD OF PROCESSING THE SAME [patent_app_type] => utility [patent_app_number] => 16/281485 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3951 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281485 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/281485
Semiconductor substrate and method of processing the same Feb 20, 2019 Issued
Array ( [id] => 16201908 [patent_doc_number] => 10727086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Optical sensor packaging system [patent_app_type] => utility [patent_app_number] => 16/281579 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 54 [patent_no_of_words] => 13340 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281579 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/281579
Optical sensor packaging system Feb 20, 2019 Issued
Array ( [id] => 16272569 [patent_doc_number] => 20200274057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => LATTICE MATCHED TUNNEL BARRIERS FOR PERPENDICULARLY MAGNETIZED HEUSLER ALLOYS [patent_app_type] => utility [patent_app_number] => 16/281642 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281642 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/281642
Lattice matched tunnel barriers for perpendicularly magnetized Heusler alloys Feb 20, 2019 Issued
Array ( [id] => 16272514 [patent_doc_number] => 20200274002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => SPLIT-GATE JFET WITH FIELD PLATE [patent_app_type] => utility [patent_app_number] => 16/281626 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4844 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281626 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/281626
Split-gate JFET with field plate Feb 20, 2019 Issued
Array ( [id] => 15331649 [patent_doc_number] => 20200006154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/281686 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14912 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281686 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/281686
Method of manufacturing a semiconductor device and a semiconductor device Feb 20, 2019 Issued
Array ( [id] => 15657285 [patent_doc_number] => 20200091173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/281334 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2085 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281334 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/281334
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Feb 20, 2019 Abandoned
Array ( [id] => 15415065 [patent_doc_number] => 20200027855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => BONDING HEAD AND METHOD FOR BONDING SEMICONDUCTOR PACKAGE, AND SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/281496 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281496 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/281496
Bonding head and method for bonding semiconductor package, and semiconductor package Feb 20, 2019 Issued
Array ( [id] => 15331651 [patent_doc_number] => 20200006155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/281679 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281679 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/281679
Method of manufacturing a semiconductor device and a semiconductor device Feb 20, 2019 Issued
Array ( [id] => 16000975 [patent_doc_number] => 20200176358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/281360 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281360 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/281360
Semiconductor device and method of manufacturing the same Feb 20, 2019 Issued
Array ( [id] => 14446425 [patent_doc_number] => 20190181086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => ISOLATION DEVICE [patent_app_type] => utility [patent_app_number] => 16/276883 [patent_app_country] => US [patent_app_date] => 2019-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16276883 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/276883
ISOLATION DEVICE Feb 14, 2019 Abandoned
Array ( [id] => 14222439 [patent_doc_number] => 20190123604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 16/220474 [patent_app_country] => US [patent_app_date] => 2018-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9195 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220474 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/220474
Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic apparatus Dec 13, 2018 Issued
Array ( [id] => 16080687 [patent_doc_number] => 20200194330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => THERMAL BUMP NETWORKS FOR INTEGRATED CIRCUIT DEVICE ASSEMBLIES [patent_app_type] => utility [patent_app_number] => 16/219158 [patent_app_country] => US [patent_app_date] => 2018-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16219158 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/219158
Thermal bump networks for integrated circuit device assemblies Dec 12, 2018 Issued
Array ( [id] => 16417917 [patent_doc_number] => 10825818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Method of forming semiconductor device [patent_app_type] => utility [patent_app_number] => 16/211239 [patent_app_country] => US [patent_app_date] => 2018-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4065 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16211239 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/211239
Method of forming semiconductor device Dec 5, 2018 Issued
Array ( [id] => 15922169 [patent_doc_number] => 10658333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Package structure and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 16/199230 [patent_app_country] => US [patent_app_date] => 2018-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7161 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16199230 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/199230
Package structure and method of fabricating the same Nov 25, 2018 Issued
Array ( [id] => 15415131 [patent_doc_number] => 20200027888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => SPLIT-GATE NON-VOLATILE MEMORY AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/199189 [patent_app_country] => US [patent_app_date] => 2018-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16199189 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/199189
Split-gate non-volatile memory and fabrication method thereof Nov 24, 2018 Issued
Array ( [id] => 15369765 [patent_doc_number] => 20200020647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => SEMICONDUCTOR CHIP MODULE INCLUDING A CHANNEL FOR CONTROLLING WARPAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/198978 [patent_app_country] => US [patent_app_date] => 2018-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8032 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16198978 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/198978
Semiconductor chip module including a channel for controlling warpage and method of manufacturing the same Nov 22, 2018 Issued
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