Search

Brittany Renee Peko

Examiner (ID: 9934)

Most Active Art Unit
3661
Art Unit(s)
3661
Total Applications
134
Issued Applications
81
Pending Applications
37
Abandoned Applications
16

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15688429 [patent_doc_number] => 20200098878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND DEVICES HAVING EPITAXIAL SOURCE OR DRAIN STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/139252 [patent_app_country] => US [patent_app_date] => 2018-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139252 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/139252
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures Sep 23, 2018 Issued
Array ( [id] => 14843573 [patent_doc_number] => 20190280187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/126349 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7603 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16126349 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/126349
Semiconductor storage device and method of manufacturing the same Sep 9, 2018 Issued
Array ( [id] => 15791583 [patent_doc_number] => 10629523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Via-based vertical capacitor and resistor structures [patent_app_type] => utility [patent_app_number] => 16/126406 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7715 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16126406 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/126406
Via-based vertical capacitor and resistor structures Sep 9, 2018 Issued
Array ( [id] => 14875427 [patent_doc_number] => 20190287955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/126018 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16126018 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/126018
Semiconductor device and method of manufacturing the same Sep 9, 2018 Issued
Array ( [id] => 15625697 [patent_doc_number] => 20200083253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => FULLY DEPLETED SEMICONDUCTOR-ON-INSULATOR TRANSISTORS WITH DIFFERENT BURIED DIELECTRIC LAYER CHARGES AND DIFFERENT THRESHOLD VOLTAGES [patent_app_type] => utility [patent_app_number] => 16/126212 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16126212 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/126212
Fully depleted semiconductor-on-insulator transistors with different buried dielectric layer charges and different threshold voltages Sep 9, 2018 Issued
Array ( [id] => 14722485 [patent_doc_number] => 20190252306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/126221 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8594 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16126221 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/126221
Printed circuit board and semiconductor package including the same Sep 9, 2018 Issued
Array ( [id] => 14691537 [patent_doc_number] => 20190244884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/126430 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16126430 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/126430
Semiconductor device Sep 9, 2018 Issued
Array ( [id] => 15823225 [patent_doc_number] => 10636809 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/126259 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5491 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16126259 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/126259
Semiconductor memory device Sep 9, 2018 Issued
Array ( [id] => 15078039 [patent_doc_number] => 10468520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Switching element and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/126220 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 9022 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16126220 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/126220
Switching element and method of manufacturing the same Sep 9, 2018 Issued
Array ( [id] => 14753203 [patent_doc_number] => 20190259775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/126209 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16126209 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/126209
Semiconductor memory device Sep 9, 2018 Issued
Array ( [id] => 14573321 [patent_doc_number] => 20190214268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/126055 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16126055 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/126055
Semiconductor device Sep 9, 2018 Issued
Array ( [id] => 13581777 [patent_doc_number] => 20180342437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => CHIP ON FILM PACKAGE AND HEAT-DISSIPATION STRUCTURE FOR A CHIP PACKAGE [patent_app_type] => utility [patent_app_number] => 16/055183 [patent_app_country] => US [patent_app_date] => 2018-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4829 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -35 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16055183 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/055183
Chip on film package and heat-dissipation structure for a chip package Aug 5, 2018 Issued
Array ( [id] => 16293637 [patent_doc_number] => 10770492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Chip scale package and related methods [patent_app_type] => utility [patent_app_number] => 16/054067 [patent_app_country] => US [patent_app_date] => 2018-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 2945 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16054067 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/054067
Chip scale package and related methods Aug 2, 2018 Issued
Array ( [id] => 13598085 [patent_doc_number] => 20180350591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => Lattice-Mismatched Semiconductor Substrates with Defect Reduction [patent_app_type] => utility [patent_app_number] => 16/045618 [patent_app_country] => US [patent_app_date] => 2018-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16045618 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/045618
Lattice-mismatched semiconductor substrates with defect reduction Jul 24, 2018 Issued
Array ( [id] => 13559291 [patent_doc_number] => 20180331193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/044581 [patent_app_country] => US [patent_app_date] => 2018-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5226 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16044581 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/044581
Semiconductor structure and manufacturing method thereof Jul 24, 2018 Issued
Array ( [id] => 15200419 [patent_doc_number] => 10497712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Semiconductor memory [patent_app_type] => utility [patent_app_number] => 16/041577 [patent_app_country] => US [patent_app_date] => 2018-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 41 [patent_no_of_words] => 16996 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16041577 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/041577
Semiconductor memory Jul 19, 2018 Issued
Array ( [id] => 13581913 [patent_doc_number] => 20180342505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => SYSTEM ON CHIP [patent_app_type] => utility [patent_app_number] => 16/037581 [patent_app_country] => US [patent_app_date] => 2018-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16037581 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/037581
System on chip Jul 16, 2018 Issued
Array ( [id] => 16202008 [patent_doc_number] => 10727188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Semiconductor device and method of forming backside openings for an ultra-thin semiconductor die [patent_app_type] => utility [patent_app_number] => 16/035838 [patent_app_country] => US [patent_app_date] => 2018-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 30 [patent_no_of_words] => 3367 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16035838 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/035838
Semiconductor device and method of forming backside openings for an ultra-thin semiconductor die Jul 15, 2018 Issued
Array ( [id] => 14955511 [patent_doc_number] => 10439035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Schottky contact structure for semiconductor devices and method for forming such Schottky contact structure [patent_app_type] => utility [patent_app_number] => 16/033500 [patent_app_country] => US [patent_app_date] => 2018-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3317 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16033500 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/033500
Schottky contact structure for semiconductor devices and method for forming such Schottky contact structure Jul 11, 2018 Issued
Array ( [id] => 13514547 [patent_doc_number] => 20180308816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => ADDING CAP TO COPPER PASSIVATION FLOW FOR ELECTROLESS PLATING [patent_app_type] => utility [patent_app_number] => 16/025126 [patent_app_country] => US [patent_app_date] => 2018-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16025126 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/025126
ADDING CAP TO COPPER PASSIVATION FLOW FOR ELECTROLESS PLATING Jul 1, 2018 Abandoned
Menu