![](/images/general/no_picture/200_user.png)
Brittany Renee Peko
Examiner (ID: 9934)
Most Active Art Unit | 3661 |
Art Unit(s) | 3661 |
Total Applications | 134 |
Issued Applications | 81 |
Pending Applications | 37 |
Abandoned Applications | 16 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 15672945
[patent_doc_number] => 10600713
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-24
[patent_title] => Semiconductor packages including a heat insulation wall
[patent_app_type] => utility
[patent_app_number] => 15/979752
[patent_app_country] => US
[patent_app_date] => 2018-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 5244
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15979752
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/979752 | Semiconductor packages including a heat insulation wall | May 14, 2018 | Issued |
Array
(
[id] => 15985067
[patent_doc_number] => 10672873
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-02
[patent_title] => Semiconductor device and method of fabricating the same
[patent_app_type] => utility
[patent_app_number] => 15/979492
[patent_app_country] => US
[patent_app_date] => 2018-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 6126
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15979492
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/979492 | Semiconductor device and method of fabricating the same | May 14, 2018 | Issued |
Array
(
[id] => 13571205
[patent_doc_number] => 20180337150
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-22
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
[patent_app_type] => utility
[patent_app_number] => 15/980033
[patent_app_country] => US
[patent_app_date] => 2018-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5022
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15980033
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/980033 | Semiconductor device and manufacture thereof | May 14, 2018 | Issued |
Array
(
[id] => 15123729
[patent_doc_number] => 20190348498
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-14
[patent_title] => MULTI-GATE SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/979123
[patent_app_country] => US
[patent_app_date] => 2018-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9757
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15979123
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/979123 | Multi-gate semiconductor device and method for forming the same | May 13, 2018 | Issued |
Array
(
[id] => 13378365
[patent_doc_number] => 20180240724
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-08-23
[patent_title] => Polymer-Based-Semiconductor Structure with Cavity
[patent_app_type] => utility
[patent_app_number] => 15/958812
[patent_app_country] => US
[patent_app_date] => 2018-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4803
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15958812
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/958812 | Polymer-based-semiconductor structure with cavity | Apr 19, 2018 | Issued |
Array
(
[id] => 15519701
[patent_doc_number] => 10566449
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-18
[patent_title] => Dual-operation depletion/enhancement mode high electron mobility transistor
[patent_app_type] => utility
[patent_app_number] => 15/958579
[patent_app_country] => US
[patent_app_date] => 2018-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 4363
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15958579
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/958579 | Dual-operation depletion/enhancement mode high electron mobility transistor | Apr 19, 2018 | Issued |
Array
(
[id] => 13271329
[patent_doc_number] => 10147751
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-12-04
[patent_title] => Edge reflection reduction
[patent_app_type] => utility
[patent_app_number] => 15/945530
[patent_app_country] => US
[patent_app_date] => 2018-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 25
[patent_no_of_words] => 4054
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15945530
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/945530 | Edge reflection reduction | Apr 3, 2018 | Issued |
Array
(
[id] => 13349817
[patent_doc_number] => 20180226448
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-08-09
[patent_title] => EDGE REFLECTION REDUCTION
[patent_app_type] => utility
[patent_app_number] => 15/945541
[patent_app_country] => US
[patent_app_date] => 2018-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4054
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15945541
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/945541 | Edge reflection reduction | Apr 3, 2018 | Issued |
Array
(
[id] => 15200577
[patent_doc_number] => 10497792
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-03
[patent_title] => Contacts for highly scaled transistors
[patent_app_type] => utility
[patent_app_number] => 15/933560
[patent_app_country] => US
[patent_app_date] => 2018-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 52
[patent_no_of_words] => 10221
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15933560
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/933560 | Contacts for highly scaled transistors | Mar 22, 2018 | Issued |
Array
(
[id] => 14367107
[patent_doc_number] => 10304867
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-28
[patent_title] => Semiconductor device and a method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 15/898975
[patent_app_country] => US
[patent_app_date] => 2018-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 22
[patent_no_of_words] => 7950
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 384
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15898975
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/898975 | Semiconductor device and a method of manufacturing the same | Feb 18, 2018 | Issued |
Array
(
[id] => 12849232
[patent_doc_number] => 20180174917
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-21
[patent_title] => FinFET Structures and Methods of Forming the Same
[patent_app_type] => utility
[patent_app_number] => 15/899185
[patent_app_country] => US
[patent_app_date] => 2018-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7318
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15899185
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/899185 | FinFET structures and methods of forming the same | Feb 18, 2018 | Issued |
Array
(
[id] => 14889097
[patent_doc_number] => 10424599
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-09-24
[patent_title] => Semiconductor structure
[patent_app_type] => utility
[patent_app_number] => 15/895430
[patent_app_country] => US
[patent_app_date] => 2018-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 5535
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15895430
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/895430 | Semiconductor structure | Feb 12, 2018 | Issued |
Array
(
[id] => 12800989
[patent_doc_number] => 20180158832
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-07
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/890062
[patent_app_country] => US
[patent_app_date] => 2018-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6073
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15890062
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/890062 | Semiconductor memory device | Feb 5, 2018 | Issued |
Array
(
[id] => 13132315
[patent_doc_number] => 10084097
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-09-25
[patent_title] => Flash memory structure
[patent_app_type] => utility
[patent_app_number] => 15/889940
[patent_app_country] => US
[patent_app_date] => 2018-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 15
[patent_no_of_words] => 7323
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15889940
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/889940 | Flash memory structure | Feb 5, 2018 | Issued |
Array
(
[id] => 14672083
[patent_doc_number] => 10373961
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-06
[patent_title] => Semiconductor device including contact structure
[patent_app_type] => utility
[patent_app_number] => 15/884504
[patent_app_country] => US
[patent_app_date] => 2018-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 43
[patent_no_of_words] => 10235
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 237
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15884504
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/884504 | Semiconductor device including contact structure | Jan 30, 2018 | Issued |
Array
(
[id] => 14252967
[patent_doc_number] => 10276692
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-04-30
[patent_title] => Fin diode structure and methods thereof
[patent_app_type] => utility
[patent_app_number] => 15/885114
[patent_app_country] => US
[patent_app_date] => 2018-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 25
[patent_no_of_words] => 9062
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885114
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/885114 | Fin diode structure and methods thereof | Jan 30, 2018 | Issued |
Array
(
[id] => 13785899
[patent_doc_number] => 20190006488
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-03
[patent_title] => GATE STRUCTURE AND METHODS THEREOF
[patent_app_type] => utility
[patent_app_number] => 15/884903
[patent_app_country] => US
[patent_app_date] => 2018-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7461
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15884903
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/884903 | Gate structure and methods thereof | Jan 30, 2018 | Issued |
Array
(
[id] => 14773231
[patent_doc_number] => 10398036
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-27
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 15/885057
[patent_app_country] => US
[patent_app_date] => 2018-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 10579
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885057
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/885057 | Semiconductor device | Jan 30, 2018 | Issued |
Array
(
[id] => 14382089
[patent_doc_number] => 20190164957
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-30
[patent_title] => STRUCTURE WITH EMBEDDED MEMORY DEVICE AND CONTACT ISOLATION SCHEME
[patent_app_type] => utility
[patent_app_number] => 15/884711
[patent_app_country] => US
[patent_app_date] => 2018-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10770
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15884711
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/884711 | Structure with embedded memory device and contact isolation scheme | Jan 30, 2018 | Issued |
Array
(
[id] => 14317103
[patent_doc_number] => 20190148255
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-16
[patent_title] => SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 15/884397
[patent_app_country] => US
[patent_app_date] => 2018-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5253
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15884397
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/884397 | Semicondcutor package and manufacturing method thereof | Jan 30, 2018 | Issued |