Search

Brittany Renee Peko

Examiner (ID: 9934)

Most Active Art Unit
3661
Art Unit(s)
3661
Total Applications
134
Issued Applications
81
Pending Applications
37
Abandoned Applications
16

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14429809 [patent_doc_number] => 10319718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Discrete capacitor and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/784985 [patent_app_country] => US [patent_app_date] => 2017-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 66 [patent_no_of_words] => 34371 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15784985 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/784985
Discrete capacitor and manufacturing method thereof Oct 15, 2017 Issued
Array ( [id] => 13006167 [patent_doc_number] => 10026758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Array substrate, manufacturing method thereof, display panel, and display device [patent_app_type] => utility [patent_app_number] => 15/782240 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 4432 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15782240 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/782240
Array substrate, manufacturing method thereof, display panel, and display device Oct 11, 2017 Issued
Array ( [id] => 14397691 [patent_doc_number] => 10312136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Etch damage and ESL free dual damascene metal interconnect [patent_app_type] => utility [patent_app_number] => 15/726590 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 4398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726590 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726590
Etch damage and ESL free dual damascene metal interconnect Oct 5, 2017 Issued
Array ( [id] => 14301091 [patent_doc_number] => 10290678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Magnetic shielding package structure for MRAM device and method for producing the same [patent_app_type] => utility [patent_app_number] => 15/716115 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2834 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15716115 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/716115
Magnetic shielding package structure for MRAM device and method for producing the same Sep 25, 2017 Issued
Array ( [id] => 12574161 [patent_doc_number] => 10020315 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-10 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 15/705514 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6346 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 431 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15705514 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/705514
Semiconductor memory device Sep 14, 2017 Issued
Array ( [id] => 13112107 [patent_doc_number] => 10074713 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-11 [patent_title] => Signal isolator integrated circuit package [patent_app_type] => utility [patent_app_number] => 15/705487 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9250 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15705487 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/705487
Signal isolator integrated circuit package Sep 14, 2017 Issued
Array ( [id] => 12759898 [patent_doc_number] => 20180145134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/706554 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 622 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706554 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/706554
Semiconductor device Sep 14, 2017 Issued
Array ( [id] => 14526039 [patent_doc_number] => 10340290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Stacked SOI semiconductor devices with back bias mechanism [patent_app_type] => utility [patent_app_number] => 15/706048 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8544 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706048 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/706048
Stacked SOI semiconductor devices with back bias mechanism Sep 14, 2017 Issued
Array ( [id] => 14079467 [patent_doc_number] => 20190088621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => Semiconductor Device and Method of Forming Embedded Die Substrate, and System-in-Package Modules with the Same [patent_app_type] => utility [patent_app_number] => 15/706584 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706584 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/706584
Semiconductor device and method of forming embedded die substrate, and system-in-package modules with the same Sep 14, 2017 Issued
Array ( [id] => 14079749 [patent_doc_number] => 20190088762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/706456 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706456 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/706456
Semiconductor device and method for manufacturing the same Sep 14, 2017 Issued
Array ( [id] => 12141081 [patent_doc_number] => 20180019164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'METHOD FOR FORMING IMPROVED LINER LAYER AND SEMICONDUCTOR DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/705426 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4339 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15705426 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/705426
Method for forming improved liner layer and semiconductor device including the same Sep 14, 2017 Issued
Array ( [id] => 14079225 [patent_doc_number] => 20190088500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => INTERCONNECTS FORMED BY A METAL REPLACEMENT PROCESS [patent_app_type] => utility [patent_app_number] => 15/705956 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15705956 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/705956
Interconnects formed by a metal replacement process Sep 14, 2017 Issued
Array ( [id] => 13740987 [patent_doc_number] => 20180374963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => TRANSCAP DEVICE ARCHITECTURE WITH REDUCED CONTROL VOLTAGE AND IMPROVED QUALITY FACTOR [patent_app_type] => utility [patent_app_number] => 15/706352 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6328 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706352 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/706352
Transcap device architecture with reduced control voltage and improved quality factor Sep 14, 2017 Issued
Array ( [id] => 13043335 [patent_doc_number] => 10043808 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-07 [patent_title] => Semiconductor memory [patent_app_type] => utility [patent_app_number] => 15/705457 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 36 [patent_no_of_words] => 15164 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15705457 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/705457
Semiconductor memory Sep 14, 2017 Issued
Array ( [id] => 12263827 [patent_doc_number] => 20180083023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'SEMICONDUCTOR MEMORY AND SEMICONDUCTOR MEMORY MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 15/706206 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7750 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706206 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/706206
Semiconductor memory and semiconductor memory manufacturing method Sep 14, 2017 Issued
Array ( [id] => 12779629 [patent_doc_number] => 20180151711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => SEMICONDUCTOR DEVICE, RC-IGBT, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/706403 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706403 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/706403
Semiconductor device, RC-IGBT, and method of manufacturing semiconductor device Sep 14, 2017 Issued
Array ( [id] => 12263936 [patent_doc_number] => 20180083132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 15/706263 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8928 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706263 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/706263
Semiconductor device Sep 14, 2017 Issued
Array ( [id] => 13420065 [patent_doc_number] => 20180261575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/706017 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706017 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/706017
Memory device Sep 14, 2017 Issued
Array ( [id] => 13598083 [patent_doc_number] => 20180350590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => Lattice-Mismatched Semiconductor Substrates With Defect Reduction [patent_app_type] => utility [patent_app_number] => 15/704992 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704992 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/704992
Lattice-mismatched semiconductor substrates with defect reduction Sep 13, 2017 Issued
Array ( [id] => 13724131 [patent_doc_number] => 20170373021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CHIPS MOUNTED OVER BOTH SURFACES OF SUBSTRATE [patent_app_type] => utility [patent_app_number] => 15/699703 [patent_app_country] => US [patent_app_date] => 2017-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15699703 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/699703
Semiconductor device including semiconductor chips mounted over both surfaces of substrate Sep 7, 2017 Issued
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