Search

Brook Kebede

Examiner (ID: 11329, Phone: (571)272-1862 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2823, 2818
Total Applications
2153
Issued Applications
1883
Pending Applications
114
Abandoned Applications
188

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1469773 [patent_doc_number] => 06406956 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Poly resistor structure for damascene metal gate' [patent_app_type] => B1 [patent_app_number] => 09/845483 [patent_app_country] => US [patent_app_date] => 2001-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 5115 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/406/06406956.pdf [firstpage_image] =>[orig_patent_app_number] => 09845483 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/845483
Poly resistor structure for damascene metal gate Apr 29, 2001 Issued
Array ( [id] => 5787424 [patent_doc_number] => 20020160574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'METHOD OF FORMING A DUAL-GATED SEMICONDUCTOR-ON-INSULATOR DEVICE' [patent_app_type] => new [patent_app_number] => 09/844184 [patent_app_country] => US [patent_app_date] => 2001-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5044 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20020160574.pdf [firstpage_image] =>[orig_patent_app_number] => 09844184 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/844184
Method of forming a dual-gated semiconductor-on-insulator device Apr 26, 2001 Issued
Array ( [id] => 1130276 [patent_doc_number] => 06787402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-07 [patent_title] => 'Double-gate vertical MOSFET transistor and fabrication method' [patent_app_type] => B1 [patent_app_number] => 09/845604 [patent_app_country] => US [patent_app_date] => 2001-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2150 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/787/06787402.pdf [firstpage_image] =>[orig_patent_app_number] => 09845604 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/845604
Double-gate vertical MOSFET transistor and fabrication method Apr 26, 2001 Issued
Array ( [id] => 1291090 [patent_doc_number] => 06630385 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'MOSFET with differential halo implant and annealing strategy' [patent_app_type] => B1 [patent_app_number] => 09/844773 [patent_app_country] => US [patent_app_date] => 2001-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1436 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/630/06630385.pdf [firstpage_image] =>[orig_patent_app_number] => 09844773 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/844773
MOSFET with differential halo implant and annealing strategy Apr 26, 2001 Issued
Array ( [id] => 1302740 [patent_doc_number] => 06620662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-16 [patent_title] => 'Double recessed transistor' [patent_app_type] => B2 [patent_app_number] => 09/836663 [patent_app_country] => US [patent_app_date] => 2001-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4904 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/620/06620662.pdf [firstpage_image] =>[orig_patent_app_number] => 09836663 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/836663
Double recessed transistor Apr 16, 2001 Issued
Array ( [id] => 1071883 [patent_doc_number] => 06841467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-11 [patent_title] => 'Method for producing semiconductor device' [patent_app_type] => utility [patent_app_number] => 09/826833 [patent_app_country] => US [patent_app_date] => 2001-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 21 [patent_no_of_words] => 4904 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/841/06841467.pdf [firstpage_image] =>[orig_patent_app_number] => 09826833 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/826833
Method for producing semiconductor device Apr 5, 2001 Issued
Array ( [id] => 1264243 [patent_doc_number] => 06660542 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Method of controlling stepper process parameters based upon optical properties of incoming process layers, and system for accomplishing same' [patent_app_type] => B1 [patent_app_number] => 09/827453 [patent_app_country] => US [patent_app_date] => 2001-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 7751 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660542.pdf [firstpage_image] =>[orig_patent_app_number] => 09827453 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/827453
Method of controlling stepper process parameters based upon optical properties of incoming process layers, and system for accomplishing same Apr 5, 2001 Issued
Array ( [id] => 6744926 [patent_doc_number] => 20030022109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Method for forming resist pattern in reverse-tapered shape' [patent_app_type] => new [patent_app_number] => 10/220394 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4482 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20030022109.pdf [firstpage_image] =>[orig_patent_app_number] => 10220394 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/220394
Method for forming resist pattern in reverse-tapered shape Mar 5, 2001 Issued
Array ( [id] => 1418518 [patent_doc_number] => 06514857 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Damascene structure fabricated using a layer of silicon-based photoresist material' [patent_app_type] => B1 [patent_app_number] => 09/788164 [patent_app_country] => US [patent_app_date] => 2001-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 28 [patent_no_of_words] => 6175 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/514/06514857.pdf [firstpage_image] =>[orig_patent_app_number] => 09788164 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/788164
Damascene structure fabricated using a layer of silicon-based photoresist material Feb 15, 2001 Issued
Array ( [id] => 6277194 [patent_doc_number] => 20020106885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'METHOD OF FABRICATING A SLOT DUAL DAMASCENE STRUCTURE WITHOUT MIDDLE STOP LAYER' [patent_app_type] => new [patent_app_number] => 09/778064 [patent_app_country] => US [patent_app_date] => 2001-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5748 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20020106885.pdf [firstpage_image] =>[orig_patent_app_number] => 09778064 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/778064
Method of fabricating a slot dual damascene structure without middle stop layer Feb 6, 2001 Issued
Array ( [id] => 1111022 [patent_doc_number] => 06806179 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-19 [patent_title] => 'Connection substrate, a method of manufacturing the connection substrate, a semiconductor device, and a method of manufacturing the semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/671884 [patent_app_country] => US [patent_app_date] => 2001-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6047 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/806/06806179.pdf [firstpage_image] =>[orig_patent_app_number] => 09671884 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/671884
Connection substrate, a method of manufacturing the connection substrate, a semiconductor device, and a method of manufacturing the semiconductor device Jan 9, 2001 Issued
Array ( [id] => 1315627 [patent_doc_number] => 06607988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-19 [patent_title] => 'Manufacturing method of semiconductor integrated circuit device' [patent_app_type] => B2 [patent_app_number] => 09/749554 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 102 [patent_figures_cnt] => 120 [patent_no_of_words] => 22754 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/607/06607988.pdf [firstpage_image] =>[orig_patent_app_number] => 09749554 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/749554
Manufacturing method of semiconductor integrated circuit device Dec 27, 2000 Issued
Array ( [id] => 1314614 [patent_doc_number] => 06614124 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Simple 4T static ram cell for low power CMOS applications' [patent_app_type] => B1 [patent_app_number] => 09/724083 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2499 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/614/06614124.pdf [firstpage_image] =>[orig_patent_app_number] => 09724083 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/724083
Simple 4T static ram cell for low power CMOS applications Nov 27, 2000 Issued
Array ( [id] => 1574666 [patent_doc_number] => 06468865 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Method of simultaneous formation of bitline isolation and periphery oxide' [patent_app_type] => B1 [patent_app_number] => 09/723653 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 7122 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/468/06468865.pdf [firstpage_image] =>[orig_patent_app_number] => 09723653 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/723653
Method of simultaneous formation of bitline isolation and periphery oxide Nov 27, 2000 Issued
Array ( [id] => 941263 [patent_doc_number] => 06969654 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-29 [patent_title] => 'Flash NVROM devices with UV charge immunity' [patent_app_type] => utility [patent_app_number] => 09/727714 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1757 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/969/06969654.pdf [firstpage_image] =>[orig_patent_app_number] => 09727714 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/727714
Flash NVROM devices with UV charge immunity Nov 27, 2000 Issued
Array ( [id] => 1390126 [patent_doc_number] => 06544854 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Silicon germanium CMOS channel' [patent_app_type] => B1 [patent_app_number] => 09/724444 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4124 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/544/06544854.pdf [firstpage_image] =>[orig_patent_app_number] => 09724444 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/724444
Silicon germanium CMOS channel Nov 27, 2000 Issued
Array ( [id] => 1209321 [patent_doc_number] => 06713363 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Method for fabricating capacitor of semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/722583 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2681 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713363.pdf [firstpage_image] =>[orig_patent_app_number] => 09722583 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/722583
Method for fabricating capacitor of semiconductor device Nov 27, 2000 Issued
Array ( [id] => 1459369 [patent_doc_number] => 06391717 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Method of manufacturing a flash memory device' [patent_app_type] => B1 [patent_app_number] => 09/721933 [patent_app_country] => US [patent_app_date] => 2000-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1470 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391717.pdf [firstpage_image] =>[orig_patent_app_number] => 09721933 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/721933
Method of manufacturing a flash memory device Nov 26, 2000 Issued
Array ( [id] => 7634799 [patent_doc_number] => 06656819 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Process for producing semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/723083 [patent_app_country] => US [patent_app_date] => 2000-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4222 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/656/06656819.pdf [firstpage_image] =>[orig_patent_app_number] => 09723083 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/723083
Process for producing semiconductor device Nov 26, 2000 Issued
Array ( [id] => 1412285 [patent_doc_number] => 06524926 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Metal-insulator-metal capacitor formed by damascene processes between metal interconnect layers and method of forming same' [patent_app_type] => B1 [patent_app_number] => 09/723434 [patent_app_country] => US [patent_app_date] => 2000-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 7538 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/524/06524926.pdf [firstpage_image] =>[orig_patent_app_number] => 09723434 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/723434
Metal-insulator-metal capacitor formed by damascene processes between metal interconnect layers and method of forming same Nov 26, 2000 Issued
Menu