Brook Kebede

Array ( [id] => 1595404 [patent_doc_number] => 06492208 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Embedded SCR protection device for output and input pad' [patent_app_type] => B1 [patent_app_number] => 09/671214 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2917 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492208.pdf [firstpage_image] =>[orig_patent_app_number] => 09671214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1375362 [patent_doc_number] => 06558988 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method for manufacturing crystalline semiconductor thin film and thin film transistor' [patent_app_type] => B1 [patent_app_number] => 09/671173 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 14668 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/558/06558988.pdf [firstpage_image] =>[orig_patent_app_number] => 09671173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1565861 [patent_doc_number] => 06376331 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/669896 [patent_app_country] => US [patent_app_date] => 2000-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 4250 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376331.pdf [firstpage_image] =>[orig_patent_app_number] => 09669896 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1478236 [patent_doc_number] => 06451708 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Method of forming contact holes in a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/670493 [patent_app_country] => US [patent_app_date] => 2000-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3981 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/451/06451708.pdf [firstpage_image] =>[orig_patent_app_number] => 09670493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1595806 [patent_doc_number] => 06492281 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Method of fabricating conductor structures with metal comb bridging avoidance' [patent_app_type] => B1 [patent_app_number] => 09/668443 [patent_app_country] => US [patent_app_date] => 2000-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3375 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492281.pdf [firstpage_image] =>[orig_patent_app_number] => 09668443 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1415347 [patent_doc_number] => 06518093 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Semiconductor device and method for manufacturing same' [patent_app_type] => B1 [patent_app_number] => 09/667124 [patent_app_country] => US [patent_app_date] => 2000-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 45 [patent_no_of_words] => 5624 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518093.pdf [firstpage_image] =>[orig_patent_app_number] => 09667124 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1193024 [patent_doc_number] => 06730597 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Pre-ECD wet surface modification to improve wettability and reduced void defect' [patent_app_type] => B1 [patent_app_number] => 09/667403 [patent_app_country] => US [patent_app_date] => 2000-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2764 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/730/06730597.pdf [firstpage_image] =>[orig_patent_app_number] => 09667403 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1359210 [patent_doc_number] => 06573191 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Insulating film forming method and insulating film forming apparatus' [patent_app_type] => B1 [patent_app_number] => 09/665664 [patent_app_country] => US [patent_app_date] => 2000-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 8090 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/573/06573191.pdf [firstpage_image] =>[orig_patent_app_number] => 09665664 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1474655 [patent_doc_number] => 06387804 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Passivation of sidewall spacers using ozonated water' [patent_app_type] => B1 [patent_app_number] => 09/664714 [patent_app_country] => US [patent_app_date] => 2000-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2839 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/387/06387804.pdf [firstpage_image] =>[orig_patent_app_number] => 09664714 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1503354 [patent_doc_number] => 06465281 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Method of manufacturing a semiconductor wafer level package' [patent_app_type] => B1 [patent_app_number] => 09/657393 [patent_app_country] => US [patent_app_date] => 2000-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2512 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465281.pdf [firstpage_image] =>[orig_patent_app_number] => 09657393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4303729 [patent_doc_number] => 06326264 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Semiconductor device and method for manufacturing same' [patent_app_type] => 1 [patent_app_number] => 9/656134 [patent_app_country] => US [patent_app_date] => 2000-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 5082 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 615 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326264.pdf [firstpage_image] =>[orig_patent_app_number] => 656134 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1391074 [patent_doc_number] => 06544908 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Ammonia gas passivation on nitride encapsulated devices' [patent_app_type] => B1 [patent_app_number] => 09/650784 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 5454 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/544/06544908.pdf [firstpage_image] =>[orig_patent_app_number] => 09650784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1585255 [patent_doc_number] => 06358755 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Ferroelectric memory device structure useful for preventing hydrogen line degradation' [patent_app_type] => B1 [patent_app_number] => 09/641091 [patent_app_country] => US [patent_app_date] => 2000-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 60 [patent_no_of_words] => 7066 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358755.pdf [firstpage_image] =>[orig_patent_app_number] => 09641091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1416711 [patent_doc_number] => 06509257 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Semiconductor device and process for making the same' [patent_app_type] => B1 [patent_app_number] => 09/633103 [patent_app_country] => US [patent_app_date] => 2000-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 41 [patent_no_of_words] => 9605 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509257.pdf [firstpage_image] =>[orig_patent_app_number] => 09633103 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1565740 [patent_doc_number] => 06376304 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Semiconductor memory device and a method for fabricating the same' [patent_app_type] => B1 [patent_app_number] => 09/608154 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 57 [patent_no_of_words] => 9000 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376304.pdf [firstpage_image] =>[orig_patent_app_number] => 09608154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1310756 [patent_doc_number] => 06613661 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Process for fabricating secure integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/607009 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3564 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/613/06613661.pdf [firstpage_image] =>[orig_patent_app_number] => 09607009 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4376915 [patent_doc_number] => 06288454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/602797 [patent_app_country] => US [patent_app_date] => 2000-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4812 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288454.pdf [firstpage_image] =>[orig_patent_app_number] => 602797 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4282340 [patent_doc_number] => 06281541 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Metal-oxide-metal capacitor for analog devices' [patent_app_type] => 1 [patent_app_number] => 9/596904 [patent_app_country] => US [patent_app_date] => 2000-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 1684 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281541.pdf [firstpage_image] =>[orig_patent_app_number] => 596904 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4366329 [patent_doc_number] => 06274456 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Monolithic device isolation by buried conducting walls' [patent_app_type] => 1 [patent_app_number] => 9/592716 [patent_app_country] => US [patent_app_date] => 2000-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2871 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274456.pdf [firstpage_image] =>[orig_patent_app_number] => 592716 [rel_patent_id] =>[rel_patent_doc_number] =>)