Search

Brook Kebede

Examiner (ID: 11329, Phone: (571)272-1862 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2823, 2818
Total Applications
2153
Issued Applications
1883
Pending Applications
114
Abandoned Applications
188

Applications

Application numberTitle of the applicationFiling DateStatus
09/451514 METHOD OF TRANSFERRING THIN FILMS OF PROCESSED MATERIALS AND PRODUCTS PRODUCED THEREFROM Nov 29, 1999 Abandoned
Array ( [id] => 4343927 [patent_doc_number] => 06284598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method of manufacturing a flash memory cell having inter-poly-dielectric isolation' [patent_app_type] => 1 [patent_app_number] => 9/447893 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3408 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284598.pdf [firstpage_image] =>[orig_patent_app_number] => 447893 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/447893
Method of manufacturing a flash memory cell having inter-poly-dielectric isolation Nov 22, 1999 Issued
Array ( [id] => 4259416 [patent_doc_number] => 06204198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Rapid thermal annealing of doped polycrystalline silicon structures formed in a single-wafer cluster tool' [patent_app_type] => 1 [patent_app_number] => 9/447174 [patent_app_country] => US [patent_app_date] => 1999-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2302 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204198.pdf [firstpage_image] =>[orig_patent_app_number] => 447174 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/447174
Rapid thermal annealing of doped polycrystalline silicon structures formed in a single-wafer cluster tool Nov 21, 1999 Issued
Array ( [id] => 4235845 [patent_doc_number] => 06165891 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer' [patent_app_type] => 1 [patent_app_number] => 9/435434 [patent_app_country] => US [patent_app_date] => 1999-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3645 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165891.pdf [firstpage_image] =>[orig_patent_app_number] => 435434 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435434
Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer Nov 21, 1999 Issued
Array ( [id] => 4101910 [patent_doc_number] => 06100161 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Method of fabrication of a raised source/drain transistor' [patent_app_type] => 1 [patent_app_number] => 9/442494 [patent_app_country] => US [patent_app_date] => 1999-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2336 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100161.pdf [firstpage_image] =>[orig_patent_app_number] => 442494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/442494
Method of fabrication of a raised source/drain transistor Nov 17, 1999 Issued
Array ( [id] => 4358656 [patent_doc_number] => 06255198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Methods of fabricating gallium nitride microelectronic layers on silicon layers and gallium nitride microelectronic structures formed thereby' [patent_app_type] => 1 [patent_app_number] => 9/441754 [patent_app_country] => US [patent_app_date] => 1999-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 49 [patent_no_of_words] => 9752 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255198.pdf [firstpage_image] =>[orig_patent_app_number] => 441754 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/441754
Methods of fabricating gallium nitride microelectronic layers on silicon layers and gallium nitride microelectronic structures formed thereby Nov 16, 1999 Issued
Array ( [id] => 4408370 [patent_doc_number] => 06309949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Semiconductor isolation process to minimize weak oxide problems' [patent_app_type] => 1 [patent_app_number] => 9/440934 [patent_app_country] => US [patent_app_date] => 1999-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2547 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/309/06309949.pdf [firstpage_image] =>[orig_patent_app_number] => 440934 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/440934
Semiconductor isolation process to minimize weak oxide problems Nov 15, 1999 Issued
Array ( [id] => 1564869 [patent_doc_number] => 06338991 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/439997 [patent_app_country] => US [patent_app_date] => 1999-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 37 [patent_no_of_words] => 13080 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/338/06338991.pdf [firstpage_image] =>[orig_patent_app_number] => 09439997 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439997
Semiconductor device and method for manufacturing the same Nov 14, 1999 Issued
Array ( [id] => 1021484 [patent_doc_number] => 06887762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-03 [patent_title] => 'Method of fabricating a field effect transistor structure with abrupt source/drain junctions' [patent_app_type] => utility [patent_app_number] => 09/831539 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5297 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/887/06887762.pdf [firstpage_image] =>[orig_patent_app_number] => 09831539 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/831539
Method of fabricating a field effect transistor structure with abrupt source/drain junctions Nov 4, 1999 Issued
Array ( [id] => 4086863 [patent_doc_number] => 06133091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Method of fabricating a lower electrode of capacitor' [patent_app_type] => 1 [patent_app_number] => 9/434688 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 2791 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133091.pdf [firstpage_image] =>[orig_patent_app_number] => 434688 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434688
Method of fabricating a lower electrode of capacitor Nov 4, 1999 Issued
Array ( [id] => 4366584 [patent_doc_number] => 06274474 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Method of forming BGA interconnections having mixed solder profiles' [patent_app_type] => 1 [patent_app_number] => 9/426578 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3338 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274474.pdf [firstpage_image] =>[orig_patent_app_number] => 426578 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/426578
Method of forming BGA interconnections having mixed solder profiles Oct 24, 1999 Issued
Array ( [id] => 4130412 [patent_doc_number] => 06146907 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Method of forming a dielectric thin film having low loss composition of Ba.sub.x Sr.sub.y Ca.sub.1-x-y TiO.sub.3 : Ba.sub.0.12-0.25 Sr.sub.0.35-0.47 Ca.sub.0.32-0.53 TiO.sub.3' [patent_app_type] => 1 [patent_app_number] => 9/420873 [patent_app_country] => US [patent_app_date] => 1999-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2867 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/146/06146907.pdf [firstpage_image] =>[orig_patent_app_number] => 420873 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/420873
Method of forming a dielectric thin film having low loss composition of Ba.sub.x Sr.sub.y Ca.sub.1-x-y TiO.sub.3 : Ba.sub.0.12-0.25 Sr.sub.0.35-0.47 Ca.sub.0.32-0.53 TiO.sub.3 Oct 18, 1999 Issued
Array ( [id] => 1602656 [patent_doc_number] => 06432835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Process for fabricating an integrated circuit device having a capacitor with an electrode formed at a high aspect ratio' [patent_app_type] => B1 [patent_app_number] => 09/411643 [patent_app_country] => US [patent_app_date] => 1999-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 53 [patent_no_of_words] => 15577 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/432/06432835.pdf [firstpage_image] =>[orig_patent_app_number] => 09411643 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/411643
Process for fabricating an integrated circuit device having a capacitor with an electrode formed at a high aspect ratio Oct 3, 1999 Issued
Array ( [id] => 4275930 [patent_doc_number] => 06281116 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/385958 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6691 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281116.pdf [firstpage_image] =>[orig_patent_app_number] => 385958 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/385958
Method of manufacturing a semiconductor device Aug 29, 1999 Issued
09/384643 SEMICONDUCTOR DEVICE WITH IMPROVED BURIED BITLINES Aug 26, 1999 Abandoned
Array ( [id] => 1441085 [patent_doc_number] => 06335282 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Method of forming a titanium comprising layer and method of forming a conductive silicide contact' [patent_app_type] => B1 [patent_app_number] => 09/383888 [patent_app_country] => US [patent_app_date] => 1999-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2273 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335282.pdf [firstpage_image] =>[orig_patent_app_number] => 09383888 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/383888
Method of forming a titanium comprising layer and method of forming a conductive silicide contact Aug 25, 1999 Issued
Array ( [id] => 4086728 [patent_doc_number] => 06133082 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Method of fabricating CMOS semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/382698 [patent_app_country] => US [patent_app_date] => 1999-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 26 [patent_no_of_words] => 12029 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 591 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133082.pdf [firstpage_image] =>[orig_patent_app_number] => 382698 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/382698
Method of fabricating CMOS semiconductor device Aug 24, 1999 Issued
Array ( [id] => 1561044 [patent_doc_number] => 06362028 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Method for fabricating TFT array and devices formed' [patent_app_type] => B1 [patent_app_number] => 09/377584 [patent_app_country] => US [patent_app_date] => 1999-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 4659 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362028.pdf [firstpage_image] =>[orig_patent_app_number] => 09377584 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/377584
Method for fabricating TFT array and devices formed Aug 18, 1999 Issued
Array ( [id] => 4408522 [patent_doc_number] => 06265294 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Integrated circuit having double bottom anti-reflective coating layer' [patent_app_type] => 1 [patent_app_number] => 9/373084 [patent_app_country] => US [patent_app_date] => 1999-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2470 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265294.pdf [firstpage_image] =>[orig_patent_app_number] => 373084 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/373084
Integrated circuit having double bottom anti-reflective coating layer Aug 11, 1999 Issued
Array ( [id] => 4152001 [patent_doc_number] => 06124167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Method for forming an etch mask during the manufacture of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/370064 [patent_app_country] => US [patent_app_date] => 1999-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3337 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124167.pdf [firstpage_image] =>[orig_patent_app_number] => 370064 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/370064
Method for forming an etch mask during the manufacture of a semiconductor device Aug 5, 1999 Issued
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