Search

Brook Kebede

Examiner (ID: 11329, Phone: (571)272-1862 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2823, 2818
Total Applications
2153
Issued Applications
1883
Pending Applications
114
Abandoned Applications
188

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5951468 [patent_doc_number] => 20020006701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-17 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING A THIN INSULATING FILM' [patent_app_type] => new [patent_app_number] => 09/359880 [patent_app_country] => US [patent_app_date] => 1999-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5247 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20020006701.pdf [firstpage_image] =>[orig_patent_app_number] => 09359880 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/359880
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING A THIN INSULATING FILM Jul 25, 1999 Abandoned
Array ( [id] => 1435872 [patent_doc_number] => 06355515 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Wiring structure of semiconductor device and method for manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/359243 [patent_app_country] => US [patent_app_date] => 1999-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4274 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355515.pdf [firstpage_image] =>[orig_patent_app_number] => 09359243 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/359243
Wiring structure of semiconductor device and method for manufacturing the same Jul 21, 1999 Issued
Array ( [id] => 4356533 [patent_doc_number] => 06190926 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Yield enhancement technique for integrated circuit processing to reduce effects of undesired dielectric moisture retention and subsequent hydrogen out-diffusion' [patent_app_type] => 1 [patent_app_number] => 9/356534 [patent_app_country] => US [patent_app_date] => 1999-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4068 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/190/06190926.pdf [firstpage_image] =>[orig_patent_app_number] => 356534 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/356534
Yield enhancement technique for integrated circuit processing to reduce effects of undesired dielectric moisture retention and subsequent hydrogen out-diffusion Jul 18, 1999 Issued
09/352198 CRYSTALLINE SEMICONDUCTOR THIN FILM, METHOD OF FABRICATING THE SAME, SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING THE SAME Jul 12, 1999 Abandoned
Array ( [id] => 4336518 [patent_doc_number] => 06189582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Small electrode for a chalcogenide switching device and method for fabricating same' [patent_app_type] => 1 [patent_app_number] => 9/344604 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 5165 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/189/06189582.pdf [firstpage_image] =>[orig_patent_app_number] => 344604 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344604
Small electrode for a chalcogenide switching device and method for fabricating same Jun 24, 1999 Issued
Array ( [id] => 7636604 [patent_doc_number] => 06380051 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Layered structure including a nitride compound semiconductor film and method for making the same' [patent_app_type] => B1 [patent_app_number] => 09/337404 [patent_app_country] => US [patent_app_date] => 1999-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 7792 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380051.pdf [firstpage_image] =>[orig_patent_app_number] => 09337404 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/337404
Layered structure including a nitride compound semiconductor film and method for making the same Jun 20, 1999 Issued
Array ( [id] => 5874157 [patent_doc_number] => 20020048962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'METHOD FOR MANUFACTURING A FUNCTIONAL DEVICE BY FORMING 45-DEGREE-SURFACE ON (100) SILICON' [patent_app_type] => new [patent_app_number] => 09/335703 [patent_app_country] => US [patent_app_date] => 1999-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6107 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20020048962.pdf [firstpage_image] =>[orig_patent_app_number] => 09335703 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/335703
Method for manufacturing a functional device by forming 45-degree-surface on (100) silicon Jun 17, 1999 Issued
Array ( [id] => 4290013 [patent_doc_number] => 06235612 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Edge bond pads on integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/324943 [patent_app_country] => US [patent_app_date] => 1999-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1158 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235612.pdf [firstpage_image] =>[orig_patent_app_number] => 324943 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/324943
Edge bond pads on integrated circuits Jun 2, 1999 Issued
Array ( [id] => 4258241 [patent_doc_number] => 06258625 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method of interconnecting electronic components using a plurality of conductive studs' [patent_app_type] => 1 [patent_app_number] => 9/315374 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2621 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258625.pdf [firstpage_image] =>[orig_patent_app_number] => 315374 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/315374
Method of interconnecting electronic components using a plurality of conductive studs May 17, 1999 Issued
Array ( [id] => 953868 [patent_doc_number] => 06958282 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-25 [patent_title] => 'SOI semiconductor configuration and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 09/313424 [patent_app_country] => US [patent_app_date] => 1999-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 29 [patent_no_of_words] => 4149 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/958/06958282.pdf [firstpage_image] =>[orig_patent_app_number] => 09313424 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/313424
SOI semiconductor configuration and method of fabricating the same May 16, 1999 Issued
Array ( [id] => 4245974 [patent_doc_number] => 06136662 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/311253 [patent_app_country] => US [patent_app_date] => 1999-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4809 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/136/06136662.pdf [firstpage_image] =>[orig_patent_app_number] => 311253 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311253
Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same May 12, 1999 Issued
Array ( [id] => 1449874 [patent_doc_number] => 06455344 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method of fabricating a planar porous silicon metal-semicoductor-metal photodetector' [patent_app_type] => B1 [patent_app_number] => 09/302120 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2692 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/455/06455344.pdf [firstpage_image] =>[orig_patent_app_number] => 09302120 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302120
Method of fabricating a planar porous silicon metal-semicoductor-metal photodetector Apr 28, 1999 Issued
Array ( [id] => 4408175 [patent_doc_number] => 06265263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Method for forming a DRAM capacitor with porous storage node and rugged sidewalls' [patent_app_type] => 1 [patent_app_number] => 9/293454 [patent_app_country] => US [patent_app_date] => 1999-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2652 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265263.pdf [firstpage_image] =>[orig_patent_app_number] => 293454 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/293454
Method for forming a DRAM capacitor with porous storage node and rugged sidewalls Apr 15, 1999 Issued
Array ( [id] => 4405681 [patent_doc_number] => 06171900 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'CVD Ta2O5/oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFET' [patent_app_type] => 1 [patent_app_number] => 9/292354 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3470 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/171/06171900.pdf [firstpage_image] =>[orig_patent_app_number] => 292354 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/292354
CVD Ta2O5/oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFET Apr 14, 1999 Issued
Array ( [id] => 1409047 [patent_doc_number] => 06528357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-04 [patent_title] => 'Method of manufacturing array substrate' [patent_app_type] => B2 [patent_app_number] => 09/266804 [patent_app_country] => US [patent_app_date] => 1999-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8072 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528357.pdf [firstpage_image] =>[orig_patent_app_number] => 09266804 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/266804
Method of manufacturing array substrate Mar 11, 1999 Issued
Array ( [id] => 1474461 [patent_doc_number] => 06387748 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Semiconductor circuit constructions, capacitor constructions, and methods of forming semiconductor circuit constructions and capacitor constructions' [patent_app_type] => B1 [patent_app_number] => 09/251104 [patent_app_country] => US [patent_app_date] => 1999-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4391 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/387/06387748.pdf [firstpage_image] =>[orig_patent_app_number] => 09251104 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/251104
Semiconductor circuit constructions, capacitor constructions, and methods of forming semiconductor circuit constructions and capacitor constructions Feb 15, 1999 Issued
Array ( [id] => 4408307 [patent_doc_number] => 06265276 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Structure and fabrication of bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 9/238703 [patent_app_country] => US [patent_app_date] => 1999-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4986 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265276.pdf [firstpage_image] =>[orig_patent_app_number] => 238703 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/238703
Structure and fabrication of bipolar transistor Jan 27, 1999 Issued
Array ( [id] => 4250455 [patent_doc_number] => 06207553 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Method of forming multiple levels of patterned metallization' [patent_app_type] => 1 [patent_app_number] => 9/237258 [patent_app_country] => US [patent_app_date] => 1999-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4910 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207553.pdf [firstpage_image] =>[orig_patent_app_number] => 237258 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/237258
Method of forming multiple levels of patterned metallization Jan 25, 1999 Issued
Array ( [id] => 1565651 [patent_doc_number] => 06376287 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method of making field effect' [patent_app_type] => B1 [patent_app_number] => 09/222609 [patent_app_country] => US [patent_app_date] => 1998-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 2943 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376287.pdf [firstpage_image] =>[orig_patent_app_number] => 09222609 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/222609
Method of making field effect Dec 28, 1998 Issued
Array ( [id] => 4401620 [patent_doc_number] => 06297555 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Method to obtain a low resistivity and conformity chemical vapor deposition titanium film' [patent_app_type] => 1 [patent_app_number] => 9/218780 [patent_app_country] => US [patent_app_date] => 1998-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4028 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297555.pdf [firstpage_image] =>[orig_patent_app_number] => 218780 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/218780
Method to obtain a low resistivity and conformity chemical vapor deposition titanium film Dec 21, 1998 Issued
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