
Brook Kebede
Examiner (ID: 11329, Phone: (571)272-1862 , Office: P/2894 )
| Most Active Art Unit | 2894 |
| Art Unit(s) | 2894, 2823, 2818 |
| Total Applications | 2153 |
| Issued Applications | 1883 |
| Pending Applications | 114 |
| Abandoned Applications | 188 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1371804
[patent_doc_number] => 06562699
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-13
[patent_title] => 'Process for manufacturing semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/202714
[patent_app_country] => US
[patent_app_date] => 1998-12-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/202714 | Process for manufacturing semiconductor device | Dec 20, 1998 | Issued |
| 09/210994 | POSITION DETECTION MARK AND POSITION DETECTION METHOD | Dec 14, 1998 | Abandoned |
Array
(
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[patent_issue_date] => 2000-12-26
[patent_title] => 'Method of manufacturing mosfet with differential gate oxide thickness on the same IC chip'
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Array
(
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[patent_issue_date] => 2000-12-05
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[patent_app_type] => 1
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Array
(
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[patent_issue_date] => 2001-02-06
[patent_title] => 'Method for fabricating a semiconductor device'
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[patent_app_country] => US
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/182173 | Method for forming a horizontal surface spacer and devices formed thereby | Oct 28, 1998 | Issued |
Array
(
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[patent_title] => 'METHOD FOR MANUFACTURING A BURIED GATE'
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Array
(
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[patent_title] => 'Method of manufacturing ferroelectric memory device useful for preventing hydrogen line degradation'
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[patent_app_number] => 9/177392
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Array
(
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[patent_issue_date] => 2001-10-25
[patent_title] => 'STRUCTURE FOR A MULTI-LAYERED DIELECTRIC LAYER AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => new
[patent_app_number] => 09/178464
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/178464 | Structure for a multi-layered dielectric layer and manufacturing method thereof | Oct 22, 1998 | Issued |
Array
(
[id] => 4249513
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[patent_title] => 'Method for forming a tantalum oxide capacitor using two-step rapid thermal nitridation'
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[patent_app_number] => 9/177841
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/177841 | Method for forming a tantalum oxide capacitor using two-step rapid thermal nitridation | Oct 21, 1998 | Issued |
Array
(
[id] => 4139190
[patent_doc_number] => 06060356
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[patent_issue_date] => 2000-05-09
[patent_title] => 'Method of fabricating virtual ground SSI flash EPROM cell and array'
[patent_app_type] => 1
[patent_app_number] => 9/175154
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[patent_app_date] => 1998-10-19
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/175154 | Method of fabricating virtual ground SSI flash EPROM cell and array | Oct 18, 1998 | Issued |
Array
(
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Array
(
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Array
(
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Array
(
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Array
(
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Array
(
[id] => 4116617
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[patent_title] => 'Process for fabricating a DRAM metal capacitor structure for use in an integrated circuit'
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Array
(
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/163062 | Monolithic inductor | Sep 28, 1998 | Issued |