Search

Brook Kebede

Examiner (ID: 11329, Phone: (571)272-1862 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2823, 2818
Total Applications
2153
Issued Applications
1883
Pending Applications
114
Abandoned Applications
188

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7063467 [patent_doc_number] => 20010042893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-22 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING MULTILEVEL MEMORY CELL AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => new [patent_app_number] => 09/161510 [patent_app_country] => US [patent_app_date] => 1998-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5980 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20010042893.pdf [firstpage_image] =>[orig_patent_app_number] => 09161510 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/161510
Semiconductor memory device having multilevel memory cell and method of manufacturing the same Sep 27, 1998 Issued
Array ( [id] => 4347659 [patent_doc_number] => 06214663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Methods of fabricating integrated circuit devices having contact pads which are separated by sidewall spacers' [patent_app_type] => 1 [patent_app_number] => 9/160781 [patent_app_country] => US [patent_app_date] => 1998-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 30 [patent_no_of_words] => 5424 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214663.pdf [firstpage_image] =>[orig_patent_app_number] => 160781 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/160781
Methods of fabricating integrated circuit devices having contact pads which are separated by sidewall spacers Sep 23, 1998 Issued
Array ( [id] => 4405317 [patent_doc_number] => 06232173 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and process for forming a new NVRAM cell structure' [patent_app_type] => 1 [patent_app_number] => 9/159470 [patent_app_country] => US [patent_app_date] => 1998-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 29 [patent_no_of_words] => 6410 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232173.pdf [firstpage_image] =>[orig_patent_app_number] => 159470 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/159470
Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and process for forming a new NVRAM cell structure Sep 22, 1998 Issued
Array ( [id] => 4408493 [patent_doc_number] => 06228697 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Method of manufacturing semiconductor device including field effect transistors' [patent_app_type] => 1 [patent_app_number] => 9/158602 [patent_app_country] => US [patent_app_date] => 1998-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 6806 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/228/06228697.pdf [firstpage_image] =>[orig_patent_app_number] => 158602 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/158602
Method of manufacturing semiconductor device including field effect transistors Sep 22, 1998 Issued
Array ( [id] => 4083892 [patent_doc_number] => 06162686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Method for forming a fuse in integrated circuit application' [patent_app_type] => 1 [patent_app_number] => 9/156362 [patent_app_country] => US [patent_app_date] => 1998-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4007 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/162/06162686.pdf [firstpage_image] =>[orig_patent_app_number] => 156362 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/156362
Method for forming a fuse in integrated circuit application Sep 17, 1998 Issued
Array ( [id] => 4291815 [patent_doc_number] => 06180448 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Semiconductor memory device having a capacitor over bitline structure and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/154783 [patent_app_country] => US [patent_app_date] => 1998-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3578 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180448.pdf [firstpage_image] =>[orig_patent_app_number] => 154783 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/154783
Semiconductor memory device having a capacitor over bitline structure and method for manufacturing the same Sep 16, 1998 Issued
Array ( [id] => 4116825 [patent_doc_number] => 06071788 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Method of manufacturing a semiconductor device with a conductor film having a polycrystalline structure' [patent_app_type] => 1 [patent_app_number] => 9/154201 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 4091 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/071/06071788.pdf [firstpage_image] =>[orig_patent_app_number] => 154201 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/154201
Method of manufacturing a semiconductor device with a conductor film having a polycrystalline structure Sep 15, 1998 Issued
Array ( [id] => 1583126 [patent_doc_number] => 06424052 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Alignment mark for electron beam lithography' [patent_app_type] => B1 [patent_app_number] => 09/154250 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2330 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424052.pdf [firstpage_image] =>[orig_patent_app_number] => 09154250 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/154250
Alignment mark for electron beam lithography Sep 15, 1998 Issued
Array ( [id] => 4124766 [patent_doc_number] => 06127221 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'In situ, one step, formation of selective hemispherical grain silicon layer, and a nitride-oxide dielectric capacitor layer, for a DRAM application' [patent_app_type] => 1 [patent_app_number] => 9/151202 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3045 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127221.pdf [firstpage_image] =>[orig_patent_app_number] => 151202 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/151202
In situ, one step, formation of selective hemispherical grain silicon layer, and a nitride-oxide dielectric capacitor layer, for a DRAM application Sep 9, 1998 Issued
Array ( [id] => 4130818 [patent_doc_number] => 06146935 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Method for forming capacitor of semiconductor device using pre-bake' [patent_app_type] => 1 [patent_app_number] => 9/148172 [patent_app_country] => US [patent_app_date] => 1998-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2230 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/146/06146935.pdf [firstpage_image] =>[orig_patent_app_number] => 148172 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/148172
Method for forming capacitor of semiconductor device using pre-bake Sep 3, 1998 Issued
Array ( [id] => 5874122 [patent_doc_number] => 20020048940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'CHEMICAL VAPOR DEPOSITION FOR SMOOTH METAL FILMS' [patent_app_type] => new [patent_app_number] => 09/146303 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4229 [patent_no_of_claims] => 80 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20020048940.pdf [firstpage_image] =>[orig_patent_app_number] => 09146303 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146303
Chemical vapor deposition for smooth metal films Sep 2, 1998 Issued
Array ( [id] => 4381652 [patent_doc_number] => 06294459 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Anti-reflective coatings and methods for forming and using same' [patent_app_type] => 1 [patent_app_number] => 9/146293 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 9150 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294459.pdf [firstpage_image] =>[orig_patent_app_number] => 146293 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146293
Anti-reflective coatings and methods for forming and using same Sep 2, 1998 Issued
Array ( [id] => 4405363 [patent_doc_number] => 06171872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method of monitoring a process of manufacturing a semiconductor wafer including hemispherical grain polysilicon' [patent_app_type] => 1 [patent_app_number] => 9/145490 [patent_app_country] => US [patent_app_date] => 1998-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3372 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/171/06171872.pdf [firstpage_image] =>[orig_patent_app_number] => 145490 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/145490
Method of monitoring a process of manufacturing a semiconductor wafer including hemispherical grain polysilicon Aug 31, 1998 Issued
Array ( [id] => 1406858 [patent_doc_number] => 06538301 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Semiconductor device and method with improved flat surface' [patent_app_type] => B1 [patent_app_number] => 09/141300 [patent_app_country] => US [patent_app_date] => 1998-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 3990 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/538/06538301.pdf [firstpage_image] =>[orig_patent_app_number] => 09141300 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/141300
Semiconductor device and method with improved flat surface Aug 26, 1998 Issued
Array ( [id] => 4131006 [patent_doc_number] => 06121083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/134394 [patent_app_country] => US [patent_app_date] => 1998-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 6614 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121083.pdf [firstpage_image] =>[orig_patent_app_number] => 134394 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/134394
Semiconductor device and method of fabricating the same Aug 13, 1998 Issued
Array ( [id] => 4329020 [patent_doc_number] => 06312997 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Low voltage high performance semiconductor devices and methods' [patent_app_type] => 1 [patent_app_number] => 9/132904 [patent_app_country] => US [patent_app_date] => 1998-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4261 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/312/06312997.pdf [firstpage_image] =>[orig_patent_app_number] => 132904 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/132904
Low voltage high performance semiconductor devices and methods Aug 11, 1998 Issued
09/129059 METALLIZING PROCESS OF SEMICONDUCTOR DEVICE Aug 3, 1998 Abandoned
09/128349 METHOD OF FABRICATING A CORONARY-TYPE CAPACITOR IN AN INTEGRATED CIRCUIT Aug 2, 1998 Abandoned
Array ( [id] => 1046791 [patent_doc_number] => 06864186 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-08 [patent_title] => 'Method of reducing surface contamination in semiconductor wet-processing vessels' [patent_app_type] => utility [patent_app_number] => 09/123430 [patent_app_country] => US [patent_app_date] => 1998-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 4207 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/864/06864186.pdf [firstpage_image] =>[orig_patent_app_number] => 09123430 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/123430
Method of reducing surface contamination in semiconductor wet-processing vessels Jul 27, 1998 Issued
Array ( [id] => 4154403 [patent_doc_number] => 06103588 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Method of forming a contact hole in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/122307 [patent_app_country] => US [patent_app_date] => 1998-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 1904 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/103/06103588.pdf [firstpage_image] =>[orig_patent_app_number] => 122307 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/122307
Method of forming a contact hole in a semiconductor device Jul 23, 1998 Issued
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