
Brook Kebede
Examiner (ID: 2450, Phone: (571)272-1862 , Office: P/2894 )
| Most Active Art Unit | 2894 |
| Art Unit(s) | 2894, 2818, 2823 |
| Total Applications | 2158 |
| Issued Applications | 1886 |
| Pending Applications | 118 |
| Abandoned Applications | 190 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16981650
[patent_doc_number] => 20210225887
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-22
[patent_title] => METAL OXIDE FILM AND METHOD FOR FORMING METAL OXIDE FILM
[patent_app_type] => utility
[patent_app_number] => 17/144550
[patent_app_country] => US
[patent_app_date] => 2021-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16764
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144550
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/144550 | Metal oxide film and method for forming metal oxide film | Jan 7, 2021 | Issued |
Array
(
[id] => 17661125
[patent_doc_number] => 20220181590
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-09
[patent_title] => DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/437296
[patent_app_country] => US
[patent_app_date] => 2020-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10927
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17437296
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/437296 | Display substrate and method of manufacturing the same, and display device | Dec 27, 2020 | Issued |
Array
(
[id] => 16779722
[patent_doc_number] => 20210116801
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-22
[patent_title] => PIXEL ARRANGEMENT STRUCTURE, ORGANIC LIGHT EMITTING DEVICE, DISPLAY DEVICE AND MASK
[patent_app_type] => utility
[patent_app_number] => 17/133052
[patent_app_country] => US
[patent_app_date] => 2020-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5423
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133052
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/133052 | Pixel arrangement structure, organic light emitting device, display device and mask | Dec 22, 2020 | Issued |
Array
(
[id] => 16762723
[patent_doc_number] => 20210108304
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-15
[patent_title] => FULL-SIZE MASK ASSEMBLY AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/130895
[patent_app_country] => US
[patent_app_date] => 2020-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8954
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17130895
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/130895 | Full-size mask assembly and manufacturing method thereof | Dec 21, 2020 | Issued |
Array
(
[id] => 19371734
[patent_doc_number] => 12063839
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-13
[patent_title] => Display substrate, display apparatus, and display substrate manufacture method
[patent_app_type] => utility
[patent_app_number] => 17/594057
[patent_app_country] => US
[patent_app_date] => 2020-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 3022
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17594057
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/594057 | Display substrate, display apparatus, and display substrate manufacture method | Dec 14, 2020 | Issued |
Array
(
[id] => 16719907
[patent_doc_number] => 20210087054
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-25
[patent_title] => SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING SAME
[patent_app_type] => utility
[patent_app_number] => 17/116021
[patent_app_country] => US
[patent_app_date] => 2020-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4512
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17116021
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/116021 | Semiconductor component and method for producing same | Dec 8, 2020 | Issued |
Array
(
[id] => 16858531
[patent_doc_number] => 20210159276
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-05-27
[patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/114155
[patent_app_country] => US
[patent_app_date] => 2020-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10093
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114155
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/114155 | 3D semiconductor device and structure | Dec 6, 2020 | Issued |
Array
(
[id] => 16920423
[patent_doc_number] => 20210193515
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-24
[patent_title] => SYSTEMS AND METHODS FOR COBALT METALIZATION
[patent_app_type] => utility
[patent_app_number] => 17/110709
[patent_app_country] => US
[patent_app_date] => 2020-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6778
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17110709
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/110709 | Systems and methods for cobalt metalization | Dec 2, 2020 | Issued |
Array
(
[id] => 18131344
[patent_doc_number] => 11557561
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-17
[patent_title] => Package structure and method of fabricating the same
[patent_app_type] => utility
[patent_app_number] => 17/106161
[patent_app_country] => US
[patent_app_date] => 2020-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 6301
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106161
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/106161 | Package structure and method of fabricating the same | Nov 28, 2020 | Issued |
Array
(
[id] => 19705146
[patent_doc_number] => 12199194
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-14
[patent_title] => Wiring base, package for storing semiconductor element, and semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/780681
[patent_app_country] => US
[patent_app_date] => 2020-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 25
[patent_no_of_words] => 8334
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17780681
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/780681 | Wiring base, package for storing semiconductor element, and semiconductor device | Nov 26, 2020 | Issued |
Array
(
[id] => 18782275
[patent_doc_number] => 11824042
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-21
[patent_title] => 3D chip sharing data bus
[patent_app_type] => utility
[patent_app_number] => 17/105272
[patent_app_country] => US
[patent_app_date] => 2020-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 31
[patent_no_of_words] => 16119
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17105272
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/105272 | 3D chip sharing data bus | Nov 24, 2020 | Issued |
Array
(
[id] => 16692158
[patent_doc_number] => 20210074637
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-11
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/103752
[patent_app_country] => US
[patent_app_date] => 2020-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6278
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103752
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/103752 | Semiconductor device | Nov 23, 2020 | Issued |
Array
(
[id] => 16752429
[patent_doc_number] => 20210104441
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-08
[patent_title] => FINFET DEVICES AND METHODS OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/100942
[patent_app_country] => US
[patent_app_date] => 2020-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5460
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17100942
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/100942 | FinFET devices and methods of forming the same | Nov 22, 2020 | Issued |
Array
(
[id] => 16752424
[patent_doc_number] => 20210104436
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-08
[patent_title] => 3D CHIP WITH SHARED CLOCK DISTRIBUTION NETWORK
[patent_app_type] => utility
[patent_app_number] => 16/953113
[patent_app_country] => US
[patent_app_date] => 2020-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15940
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953113
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/953113 | 3D chip with shared clock distribution network | Nov 18, 2020 | Issued |
Array
(
[id] => 18593302
[patent_doc_number] => 11742213
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-29
[patent_title] => Methods for forming polycrystalline channel on dielectric films with controlled grain boundaries
[patent_app_type] => utility
[patent_app_number] => 17/098052
[patent_app_country] => US
[patent_app_date] => 2020-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 22
[patent_no_of_words] => 6986
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17098052
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/098052 | Methods for forming polycrystalline channel on dielectric films with controlled grain boundaries | Nov 12, 2020 | Issued |
Array
(
[id] => 18112867
[patent_doc_number] => 20230005747
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-05
[patent_title] => METHOD FOR FORMING AN ELECTRICAL CONTACT AND METHOD FOR FORMING A SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/774063
[patent_app_country] => US
[patent_app_date] => 2020-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2758
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17774063
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/774063 | Method for forming an electrical contact and method for forming a semiconductor device | Nov 4, 2020 | Issued |
Array
(
[id] => 19370485
[patent_doc_number] => 12062579
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-13
[patent_title] => Method of simultaneous silicidation on source and drain of NMOS and PMOS transistors
[patent_app_type] => utility
[patent_app_number] => 17/085850
[patent_app_country] => US
[patent_app_date] => 2020-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 27
[patent_no_of_words] => 10597
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085850
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/085850 | Method of simultaneous silicidation on source and drain of NMOS and PMOS transistors | Oct 29, 2020 | Issued |
Array
(
[id] => 17523043
[patent_doc_number] => 20220108892
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-07
[patent_title] => BORON CONCENTRATION TUNABILITY IN BORON-SILICON FILMS
[patent_app_type] => utility
[patent_app_number] => 17/063339
[patent_app_country] => US
[patent_app_date] => 2020-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7994
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17063339
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/063339 | Boron concentration tunability in boron-silicon films | Oct 4, 2020 | Issued |
Array
(
[id] => 18029079
[patent_doc_number] => 11512254
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-29
[patent_title] => Quantum dots, and an electronic device including the same
[patent_app_type] => utility
[patent_app_number] => 17/036122
[patent_app_country] => US
[patent_app_date] => 2020-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 12834
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036122
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/036122 | Quantum dots, and an electronic device including the same | Sep 28, 2020 | Issued |
Array
(
[id] => 19093851
[patent_doc_number] => 11955316
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-09
[patent_title] => Substrate processing method, method for manufacturing semiconducor device, and plasma processing apparatus
[patent_app_type] => utility
[patent_app_number] => 17/035899
[patent_app_country] => US
[patent_app_date] => 2020-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6935
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17035899
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/035899 | Substrate processing method, method for manufacturing semiconducor device, and plasma processing apparatus | Sep 28, 2020 | Issued |