Brook Kebede

Array ( [id] => 13435171 [patent_doc_number] => 20180269128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => COMPUTING SYSTEM WITH A THERMAL INTERFACE COMPRISING MAGNETIC PARTICLES [patent_app_type] => utility [patent_app_number] => 15/461033 [patent_app_country] => US [patent_app_date] => 2017-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15461033 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12498801 [patent_doc_number] => 09997562 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-12 [patent_title] => Mram memory device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/458944 [patent_app_country] => US [patent_app_date] => 2017-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10926 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15458944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13653585 [patent_doc_number] => 09853114 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-26 [patent_title] => Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/458655 [patent_app_country] => US [patent_app_date] => 2017-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 8264 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15458655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16332673 [patent_doc_number] => 20200303639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => MEMORY DEVICE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/085555 [patent_app_country] => US [patent_app_date] => 2017-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16085555 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13435277 [patent_doc_number] => 20180269181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => System -in-Package with Double-Sided Molding [patent_app_type] => utility [patent_app_number] => 15/458649 [patent_app_country] => US [patent_app_date] => 2017-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15458649 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11967410 [patent_doc_number] => 20170271563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'METHOD AND APPARATUS FOR CONTROLLED SEMICONDUCTOR GROWTH DURING SYNTHESIS OF QUANTUM DOT MATERIALS' [patent_app_type] => utility [patent_app_number] => 15/458882 [patent_app_country] => US [patent_app_date] => 2017-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9230 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15458882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11710424 [patent_doc_number] => 20170178924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'OXIDE ETCH SELECTIVITY ENHANCEMENT' [patent_app_type] => utility [patent_app_number] => 15/453786 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6460 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15453786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11952291 [patent_doc_number] => 20170256442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'SEMICONDUCTOR ON INSULATOR STRUCTURE COMPRISING A SACRIFICIAL LAYER AND METHOD OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 15/450124 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9854 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450124 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14317753 [patent_doc_number] => 20190148580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => IONIZING RADIATION SENSOR BASED ON FLOAT-ZONE SILICON WITH P-TYPE CONDUCTIVITY [patent_app_type] => utility [patent_app_number] => 16/302679 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16302679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13755491 [patent_doc_number] => 10170701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Controlled deposition of materials using a differential pressure regime [patent_app_type] => utility [patent_app_number] => 15/449946 [patent_app_country] => US [patent_app_date] => 2017-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6228 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15449946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12969346 [patent_doc_number] => 09876022 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-23 [patent_title] => Method for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 15/449689 [patent_app_country] => US [patent_app_date] => 2017-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2513 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15449689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13405425 [patent_doc_number] => 20180254255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => METHOD FOR PRODUCING SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 15/449361 [patent_app_country] => US [patent_app_date] => 2017-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15449361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12779086 [patent_doc_number] => 20180151530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 15/449321 [patent_app_country] => US [patent_app_date] => 2017-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8375 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15449321 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12615138 [patent_doc_number] => 20180096876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => Support Apparatus and Support Method [patent_app_type] => utility [patent_app_number] => 15/558378 [patent_app_country] => US [patent_app_date] => 2017-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6124 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15558378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11623368 [patent_doc_number] => 20170133556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'LIGHT EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 15/410441 [patent_app_country] => US [patent_app_date] => 2017-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6834 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15410441 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17077925 [patent_doc_number] => 11114340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Method for producing an interconnection comprising a via extending through a substrate [patent_app_type] => utility [patent_app_number] => 16/070506 [patent_app_country] => US [patent_app_date] => 2017-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3940 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16070506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13057241 [patent_doc_number] => 10050019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Method of manufacturing wafer level package and wafer level package manufactured thereby [patent_app_type] => utility [patent_app_number] => 15/405619 [patent_app_country] => US [patent_app_date] => 2017-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 6449 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15405619 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13306533 [patent_doc_number] => 20180204803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => INTERCONNECT STRUCTURE WITH NITRIDED BARRIER [patent_app_type] => utility [patent_app_number] => 15/405711 [patent_app_country] => US [patent_app_date] => 2017-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15405711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13071385 [patent_doc_number] => 10056481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-21 [patent_title] => Semiconductor device structure [patent_app_type] => utility [patent_app_number] => 15/405495 [patent_app_country] => US [patent_app_date] => 2017-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15405495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14252571 [patent_doc_number] => 10276492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Method for fabricating semiconductor structures including a high resistivity layer, and related semiconductor structures [patent_app_type] => utility [patent_app_number] => 15/405867 [patent_app_country] => US [patent_app_date] => 2017-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5803 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15405867 [rel_patent_id] =>[rel_patent_doc_number] =>)