
Bruce Edward Snow
Examiner (ID: 12379, Phone: (571)272-4759 , Office: P/3738 )
| Most Active Art Unit | 3738 |
| Art Unit(s) | 3738, 3308, 3774 |
| Total Applications | 2108 |
| Issued Applications | 1478 |
| Pending Applications | 201 |
| Abandoned Applications | 471 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20087116
[patent_doc_number] => 20250217052
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-03
[patent_title] => Charge Domain Compute-in-DRAM for Binary Neural Network
[patent_app_type] => utility
[patent_app_number] => 18/761148
[patent_app_country] => US
[patent_app_date] => 2024-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1094
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18761148
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/761148 | Charge Domain Compute-in-DRAM for Binary Neural Network | Jun 30, 2024 | Pending |
Array
(
[id] => 19530104
[patent_doc_number] => 20240354006
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => APPARATUS WITH RESPONSE COMPLETION PACING
[patent_app_type] => utility
[patent_app_number] => 18/759793
[patent_app_country] => US
[patent_app_date] => 2024-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6175
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18759793
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/759793 | Apparatus with response completion pacing | Jun 27, 2024 | Issued |
Array
(
[id] => 19499303
[patent_doc_number] => 20240338321
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-10
[patent_title] => STORE-TO-LOAD FORWARDING FOR PROCESSOR PIPELINES
[patent_app_type] => utility
[patent_app_number] => 18/747414
[patent_app_country] => US
[patent_app_date] => 2024-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10255
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747414
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/747414 | STORE-TO-LOAD FORWARDING FOR PROCESSOR PIPELINES | Jun 17, 2024 | Pending |
Array
(
[id] => 19481820
[patent_doc_number] => 20240329862
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => MEMORY DEVICE AND OPERATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/739263
[patent_app_country] => US
[patent_app_date] => 2024-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8440
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739263
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/739263 | Memory device and operation method thereof | Jun 9, 2024 | Issued |
Array
(
[id] => 19645075
[patent_doc_number] => 20240419595
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-19
[patent_title] => COHERENT HIERARCHICAL CACHE LINE TRACKING
[patent_app_type] => utility
[patent_app_number] => 18/734006
[patent_app_country] => US
[patent_app_date] => 2024-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19612
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18734006
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/734006 | COHERENT HIERARCHICAL CACHE LINE TRACKING | Jun 4, 2024 | Pending |
Array
(
[id] => 20304200
[patent_doc_number] => 12450188
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-21
[patent_title] => System and method for providing in-storage acceleration (ISA) in data storage devices
[patent_app_type] => utility
[patent_app_number] => 18/677697
[patent_app_country] => US
[patent_app_date] => 2024-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3661
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677697
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/677697 | System and method for providing in-storage acceleration (ISA) in data storage devices | May 28, 2024 | Issued |
Array
(
[id] => 20395444
[patent_doc_number] => 20250370919
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-12-04
[patent_title] => SOCKET CONNECTIONS AMONG PROCESSING-ELEMENT BANKS AND CHIPS
[patent_app_type] => utility
[patent_app_number] => 18/675734
[patent_app_country] => US
[patent_app_date] => 2024-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675734
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/675734 | SOCKET CONNECTIONS AMONG PROCESSING-ELEMENT BANKS AND CHIPS | May 27, 2024 | Pending |
Array
(
[id] => 19452380
[patent_doc_number] => 20240312510
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => MEMORY SYSTEM, CONTROL METHOD, AND POWER CONTROL CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/671775
[patent_app_country] => US
[patent_app_date] => 2024-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8674
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18671775
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/671775 | Memory system, control method, and power control circuit | May 21, 2024 | Issued |
Array
(
[id] => 19391276
[patent_doc_number] => 20240281146
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-22
[patent_title] => Method and Apparatus for Allocating Data Storage Space
[patent_app_type] => utility
[patent_app_number] => 18/650866
[patent_app_country] => US
[patent_app_date] => 2024-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9471
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650866
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/650866 | Method and apparatus for allocating data storage space | Apr 29, 2024 | Issued |
Array
(
[id] => 19811345
[patent_doc_number] => 12242739
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-04
[patent_title] => Transparently attached flash memory security
[patent_app_type] => utility
[patent_app_number] => 18/651280
[patent_app_country] => US
[patent_app_date] => 2024-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 12160
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 251
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18651280
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/651280 | Transparently attached flash memory security | Apr 29, 2024 | Issued |
Array
(
[id] => 20310829
[patent_doc_number] => 20250328458
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-23
[patent_title] => Data Storage Device and Method for Data Processing Optimization for Computational Storage
[patent_app_type] => utility
[patent_app_number] => 18/640166
[patent_app_country] => US
[patent_app_date] => 2024-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 39
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18640166
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/640166 | Data Storage Device and Method for Data Processing Optimization for Computational Storage | Apr 18, 2024 | Pending |
Array
(
[id] => 20109967
[patent_doc_number] => 12360688
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-15
[patent_title] => Transistor configurations for vertical memory arrays
[patent_app_type] => utility
[patent_app_number] => 18/638480
[patent_app_country] => US
[patent_app_date] => 2024-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 10771
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18638480
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/638480 | Transistor configurations for vertical memory arrays | Apr 16, 2024 | Issued |
Array
(
[id] => 20110190
[patent_doc_number] => 12360911
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-15
[patent_title] => Cache purging in a distributed networked system
[patent_app_type] => utility
[patent_app_number] => 18/636032
[patent_app_country] => US
[patent_app_date] => 2024-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 5964
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18636032
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/636032 | Cache purging in a distributed networked system | Apr 14, 2024 | Issued |
Array
(
[id] => 19530350
[patent_doc_number] => 20240354252
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => CACHE MEMORY DEVICE AND METHOD FOR IMPLEMENTING CACHE SCHEDULING USING SAME
[patent_app_type] => utility
[patent_app_number] => 18/634662
[patent_app_country] => US
[patent_app_date] => 2024-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7346
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634662
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/634662 | Cache memory device and method for implementing cache scheduling using same | Apr 11, 2024 | Issued |
Array
(
[id] => 20234413
[patent_doc_number] => 20250291732
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-18
[patent_title] => DATA TRANSFER TECHNIQUE
[patent_app_type] => utility
[patent_app_number] => 18/634643
[patent_app_country] => US
[patent_app_date] => 2024-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 51667
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 32
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634643
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/634643 | DATA TRANSFER TECHNIQUE | Apr 11, 2024 | Pending |
Array
(
[id] => 19514259
[patent_doc_number] => 20240345945
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-17
[patent_title] => CALCULATION PROCESSING APPARATUS AND CALCULATION PROCESSING METHOD
[patent_app_type] => utility
[patent_app_number] => 18/633240
[patent_app_country] => US
[patent_app_date] => 2024-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7964
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18633240
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/633240 | CALCULATION PROCESSING APPARATUS AND CALCULATION PROCESSING METHOD | Apr 10, 2024 | Issued |
Array
(
[id] => 19334421
[patent_doc_number] => 20240248851
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-25
[patent_title] => PROCESSOR-BASED SYSTEM FOR ALLOCATING CACHE LINES TO A HIGHER-LEVEL CACHE MEMORY
[patent_app_type] => utility
[patent_app_number] => 18/624301
[patent_app_country] => US
[patent_app_date] => 2024-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11761
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624301
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/624301 | Processor-based system for allocating cache lines to a higher-level cache memory | Apr 1, 2024 | Issued |
Array
(
[id] => 20304184
[patent_doc_number] => 12450172
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-21
[patent_title] => Reducing set of policies with two or more hyper-dimensions
[patent_app_type] => utility
[patent_app_number] => 18/623103
[patent_app_country] => US
[patent_app_date] => 2024-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 34
[patent_no_of_words] => 19736
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623103
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/623103 | Reducing set of policies with two or more hyper-dimensions | Mar 31, 2024 | Issued |
Array
(
[id] => 20304183
[patent_doc_number] => 12450171
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-21
[patent_title] => Cache replacement system
[patent_app_type] => utility
[patent_app_number] => 18/623099
[patent_app_country] => US
[patent_app_date] => 2024-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 34
[patent_no_of_words] => 19345
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623099
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/623099 | Cache replacement system | Mar 31, 2024 | Issued |
Array
(
[id] => 19303038
[patent_doc_number] => 20240231617
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-11
[patent_title] => MEMORY DEVICE PROGRAMMING TECHNIQUE FOR INCREASED BITS PER CELL
[patent_app_type] => utility
[patent_app_number] => 18/612028
[patent_app_country] => US
[patent_app_date] => 2024-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17573
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612028
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/612028 | Memory device programming technique for increased bits per cell | Mar 20, 2024 | Issued |