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Bruce Edward Snow

Examiner (ID: 12379, Phone: (571)272-4759 , Office: P/3738 )

Most Active Art Unit
3738
Art Unit(s)
3738, 3308, 3774
Total Applications
2108
Issued Applications
1478
Pending Applications
201
Abandoned Applications
471

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19971491 [patent_doc_number] => 12340106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Storage device for storing address information of target page with overwritten dummy data and operating method thereof [patent_app_type] => utility [patent_app_number] => 18/344545 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2321 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344545 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344545
Storage device for storing address information of target page with overwritten dummy data and operating method thereof Jun 28, 2023 Issued
Array ( [id] => 18727758 [patent_doc_number] => 20230342051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/343835 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25756 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18343835 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/343835
Memory storage with selected performance mode Jun 28, 2023 Issued
Array ( [id] => 19811004 [patent_doc_number] => 12242396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => PC-based memory permissions [patent_app_type] => utility [patent_app_number] => 18/343125 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 18341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18343125 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/343125
PC-based memory permissions Jun 27, 2023 Issued
Array ( [id] => 18819649 [patent_doc_number] => 20230393989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => TECHNIQUES FOR STORING DATA AND TAGS IN DIFFERENT MEMORY ARRAYS [patent_app_type] => utility [patent_app_number] => 18/209967 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18209967 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/209967
Techniques for storing data and tags in different memory arrays Jun 13, 2023 Issued
Array ( [id] => 19764575 [patent_doc_number] => 12222865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Cache for identifiers representing merged access control information [patent_app_type] => utility [patent_app_number] => 18/325355 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7861 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18325355 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/325355
Cache for identifiers representing merged access control information May 29, 2023 Issued
Array ( [id] => 18772884 [patent_doc_number] => 20230367710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => DATA DEFRAGMENTATION CONTROL [patent_app_type] => utility [patent_app_number] => 18/197469 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197469 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/197469
Data defragmentation control May 14, 2023 Issued
Array ( [id] => 19369470 [patent_doc_number] => 12061552 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Application of a default shared state cache coherency protocol [patent_app_type] => utility [patent_app_number] => 18/315806 [patent_app_country] => US [patent_app_date] => 2023-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8910 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18315806 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/315806
Application of a default shared state cache coherency protocol May 10, 2023 Issued
Array ( [id] => 19538493 [patent_doc_number] => 12131046 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-29 [patent_title] => Clone volume split of clone volume from parent volume with data tiered to object store [patent_app_type] => utility [patent_app_number] => 18/308703 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6735 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18308703 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/308703
Clone volume split of clone volume from parent volume with data tiered to object store Apr 27, 2023 Issued
Array ( [id] => 19514066 [patent_doc_number] => 20240345752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => PROTECTING DATA FROM UNPRIVILEGED PROCESSES [patent_app_type] => utility [patent_app_number] => 18/301851 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10497 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301851 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/301851
Protecting data from unprivileged processes Apr 16, 2023 Issued
Array ( [id] => 19514219 [patent_doc_number] => 20240345905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => EXPLAINABLE CLASSIFICATIONS WITH ABSTENTION USING CLIENT AGNOSTIC MACHINE LEARNING MODELS [patent_app_type] => utility [patent_app_number] => 18/300688 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14497 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18300688 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/300688
EXPLAINABLE CLASSIFICATIONS WITH ABSTENTION USING CLIENT AGNOSTIC MACHINE LEARNING MODELS Apr 13, 2023 Pending
Array ( [id] => 19405540 [patent_doc_number] => 20240289051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => MAPPING TABLE UPDATING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT [patent_app_type] => utility [patent_app_number] => 18/190152 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9448 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18190152 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/190152
Mapping table updating method, memory storage device and memory control circuit unit Mar 26, 2023 Issued
Array ( [id] => 18513730 [patent_doc_number] => 20230229967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => RECORDING MEDIUM, MACHINE LEARNING METHOD, AND MACHINE LEARNING DEVICE [patent_app_type] => utility [patent_app_number] => 18/124630 [patent_app_country] => US [patent_app_date] => 2023-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18124630 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/124630
RECORDING MEDIUM, MACHINE LEARNING METHOD, AND MACHINE LEARNING DEVICE Mar 21, 2023 Pending
Array ( [id] => 18889477 [patent_doc_number] => 11868247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-09 [patent_title] => Storage system with multiplane segments and cooperative flash management [patent_app_type] => utility [patent_app_number] => 18/124514 [patent_app_country] => US [patent_app_date] => 2023-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 37 [patent_no_of_words] => 37326 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18124514 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/124514
Storage system with multiplane segments and cooperative flash management Mar 20, 2023 Issued
Array ( [id] => 19434701 [patent_doc_number] => 20240303199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => CACHING TECHNIQUES USING A MAPPING CACHE AND MAINTAINING CACHE COHERENCY USING PHYSICAL TO LOGICAL ADDRESS MAPPING [patent_app_type] => utility [patent_app_number] => 18/119565 [patent_app_country] => US [patent_app_date] => 2023-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18119565 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/119565
Caching techniques using a mapping cache and maintaining cache coherency using physical to logical address mapping Mar 8, 2023 Issued
Array ( [id] => 19434705 [patent_doc_number] => 20240303203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => CACHE MANAGEMENT USING EVICTION PRIORITY BASED ON MEMORY REUSE [patent_app_type] => utility [patent_app_number] => 18/180008 [patent_app_country] => US [patent_app_date] => 2023-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23920 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18180008 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/180008
Cache management using eviction priority based on memory reuse Mar 6, 2023 Issued
Array ( [id] => 19522985 [patent_doc_number] => 12124712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Storage system [patent_app_type] => utility [patent_app_number] => 18/179563 [patent_app_country] => US [patent_app_date] => 2023-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10343 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18179563 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/179563
Storage system Mar 6, 2023 Issued
Array ( [id] => 18819648 [patent_doc_number] => 20230393988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => ARITHMETIC PROCESSING DEVICE AND ARITHMETIC PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 18/178568 [patent_app_country] => US [patent_app_date] => 2023-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14496 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18178568 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/178568
Arithmetic processing device and arithmetic processing method Mar 5, 2023 Issued
Array ( [id] => 19413331 [patent_doc_number] => 12079147 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Memory device for efficiently determining whether to perform re-training operation and memory system including the same [patent_app_type] => utility [patent_app_number] => 18/170949 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 36 [patent_no_of_words] => 13705 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170949 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170949
Memory device for efficiently determining whether to perform re-training operation and memory system including the same Feb 16, 2023 Issued
Array ( [id] => 19442920 [patent_doc_number] => 12093184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Processor-based system for allocating cache lines to a higher-level cache memory [patent_app_type] => utility [patent_app_number] => 18/169852 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 11715 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18169852 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/169852
Processor-based system for allocating cache lines to a higher-level cache memory Feb 14, 2023 Issued
Array ( [id] => 19212635 [patent_doc_number] => 12001698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Memory system and SoC including linear address remapping logic [patent_app_type] => utility [patent_app_number] => 18/105967 [patent_app_country] => US [patent_app_date] => 2023-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7583 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18105967 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/105967
Memory system and SoC including linear address remapping logic Feb 5, 2023 Issued
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