Search

Bryan Bui

Examiner (ID: 11867, Phone: (571)272-2271 , Office: P/2865 )

Most Active Art Unit
2863
Art Unit(s)
2414, 2863, 2764, 2857, 2865
Total Applications
2284
Issued Applications
2045
Pending Applications
88
Abandoned Applications
151

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9360369 [patent_doc_number] => 20140070241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'SOLID STATE LIGHT SOURCE ARRAY' [patent_app_type] => utility [patent_app_number] => 14/078563 [patent_app_country] => US [patent_app_date] => 2013-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3114 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14078563 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/078563
SOLID STATE LIGHT SOURCE ARRAY Nov 12, 2013 Abandoned
Array ( [id] => 11549866 [patent_doc_number] => 09618709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-11 [patent_title] => 'Hybrid integration of edge-coupled chips' [patent_app_type] => utility [patent_app_number] => 14/060136 [patent_app_country] => US [patent_app_date] => 2013-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5988 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14060136 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/060136
Hybrid integration of edge-coupled chips Oct 21, 2013 Issued
Array ( [id] => 10638694 [patent_doc_number] => 09356208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-31 [patent_title] => 'Manufacturing method of pixel structure' [patent_app_type] => utility [patent_app_number] => 14/038774 [patent_app_country] => US [patent_app_date] => 2013-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4125 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14038774 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/038774
Manufacturing method of pixel structure Sep 26, 2013 Issued
Array ( [id] => 10343853 [patent_doc_number] => 20150228858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'OPTOELECTRONIC COMPONENT WITH A LAYER STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/427687 [patent_app_country] => US [patent_app_date] => 2013-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3552 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14427687 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/427687
Optoelectronic component with a layer structure Sep 24, 2013 Issued
Array ( [id] => 9223083 [patent_doc_number] => 20140017859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'METHOD FOR FABRICATING TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN' [patent_app_type] => utility [patent_app_number] => 14/029199 [patent_app_country] => US [patent_app_date] => 2013-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6206 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14029199 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/029199
METHOD FOR FABRICATING TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN Sep 16, 2013 Abandoned
Array ( [id] => 10343841 [patent_doc_number] => 20150228847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'HIGH-LUMINANCE NITRIDE LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 14/428124 [patent_app_country] => US [patent_app_date] => 2013-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14428124 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/428124
HIGH-LUMINANCE NITRIDE LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME Sep 12, 2013 Abandoned
Array ( [id] => 9191627 [patent_doc_number] => 20130330942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-12 [patent_title] => 'COMPLIANT CONDUCTIVE NANO-PARTICLE ELECTRICAL INTERCONNECT' [patent_app_type] => utility [patent_app_number] => 13/969953 [patent_app_country] => US [patent_app_date] => 2013-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6606 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13969953 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/969953
Compliant conductive nano-particle electrical interconnect Aug 18, 2013 Issued
Array ( [id] => 11862274 [patent_doc_number] => 09741970 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Method of manufacturing organic light emitting display' [patent_app_type] => utility [patent_app_number] => 13/935463 [patent_app_country] => US [patent_app_date] => 2013-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 6159 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13935463 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/935463
Method of manufacturing organic light emitting display Jul 2, 2013 Issued
Array ( [id] => 9212195 [patent_doc_number] => 20140011372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'FILM DEPOSITION METHOD' [patent_app_type] => utility [patent_app_number] => 13/934677 [patent_app_country] => US [patent_app_date] => 2013-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9841 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13934677 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/934677
FILM DEPOSITION METHOD Jul 2, 2013 Abandoned
Array ( [id] => 11615613 [patent_doc_number] => 09653476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'On-SOI integrated circuit comprising a lateral diode for protection against electrostatic discharges' [patent_app_type] => utility [patent_app_number] => 13/933441 [patent_app_country] => US [patent_app_date] => 2013-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 24 [patent_no_of_words] => 7013 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13933441 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/933441
On-SOI integrated circuit comprising a lateral diode for protection against electrostatic discharges Jul 1, 2013 Issued
Array ( [id] => 9212194 [patent_doc_number] => 20140011371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'SILICON OXIDE FILM FORMING METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/933902 [patent_app_country] => US [patent_app_date] => 2013-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4205 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13933902 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/933902
SILICON OXIDE FILM FORMING METHOD AND APPARATUS Jul 1, 2013 Abandoned
Array ( [id] => 9223096 [patent_doc_number] => 20140017871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'Integrated circuit on SOI comprising a bipolar transistor with isolating trenches of distinct depths' [patent_app_type] => utility [patent_app_number] => 13/933396 [patent_app_country] => US [patent_app_date] => 2013-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3340 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13933396 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/933396
Integrated circuit on SOI comprising a bipolar transistor with isolating trenches of distinct depths Jul 1, 2013 Issued
Array ( [id] => 9223081 [patent_doc_number] => 20140017856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'On-SOI integrated circuit comprising a subjacent protection transistor' [patent_app_type] => utility [patent_app_number] => 13/933379 [patent_app_country] => US [patent_app_date] => 2013-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4298 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13933379 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/933379
On-SOI integrated circuit comprising a subjacent protection transistor Jul 1, 2013 Issued
Array ( [id] => 9789643 [patent_doc_number] => 20150001587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'METHODS OF FORMING GROUP III-V SEMICONDUCTOR MATERIALS ON GROUP IV SUBSTRATES AND THE RESULTING SUBSTRATE STRUCTURES' [patent_app_type] => utility [patent_app_number] => 13/927685 [patent_app_country] => US [patent_app_date] => 2013-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4757 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13927685 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/927685
Methods of forming group III-V semiconductor materials on group IV substrates and the resulting substrate structures Jun 25, 2013 Issued
Array ( [id] => 13145799 [patent_doc_number] => 10090239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Metal-insulator-metal on-die capacitor with partial vias [patent_app_type] => utility [patent_app_number] => 14/411384 [patent_app_country] => US [patent_app_date] => 2013-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14411384 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/411384
Metal-insulator-metal on-die capacitor with partial vias Jun 25, 2013 Issued
Array ( [id] => 10964821 [patent_doc_number] => 20140367854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-18 [patent_title] => 'INTERCONNECT STRUCTURE FOR MOLDED IC PACKAGES' [patent_app_type] => utility [patent_app_number] => 13/927470 [patent_app_country] => US [patent_app_date] => 2013-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6101 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13927470 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/927470
INTERCONNECT STRUCTURE FOR MOLDED IC PACKAGES Jun 25, 2013 Abandoned
Array ( [id] => 9789784 [patent_doc_number] => 20150001728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'PRE-TREATMENT METHOD FOR METAL-OXIDE REDUCTION AND DEVICE FORMED' [patent_app_type] => utility [patent_app_number] => 13/927570 [patent_app_country] => US [patent_app_date] => 2013-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5743 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13927570 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/927570
PRE-TREATMENT METHOD FOR METAL-OXIDE REDUCTION AND DEVICE FORMED Jun 25, 2013 Abandoned
Array ( [id] => 11807365 [patent_doc_number] => 09548449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-17 [patent_title] => 'Conductive oxide random access memory (CORAM) cell and method of fabricating same' [patent_app_type] => utility [patent_app_number] => 13/925951 [patent_app_country] => US [patent_app_date] => 2013-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5385 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13925951 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/925951
Conductive oxide random access memory (CORAM) cell and method of fabricating same Jun 24, 2013 Issued
Array ( [id] => 10971880 [patent_doc_number] => 20140374915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'INTEGRATION OF OPTICAL COMPONENTS IN INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/925916 [patent_app_country] => US [patent_app_date] => 2013-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2483 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13925916 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/925916
Integration of optical components in integrated circuits Jun 24, 2013 Issued
Array ( [id] => 10971878 [patent_doc_number] => 20140374913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'CIRCUIT ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/925900 [patent_app_country] => US [patent_app_date] => 2013-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8293 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13925900 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/925900
Circuit arrangement and method for manufacturing the same Jun 24, 2013 Issued
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