Bryan Bui
Examiner (ID: 11867, Phone: (571)272-2271 , Office: P/2865 )
Most Active Art Unit | 2863 |
Art Unit(s) | 2414, 2863, 2764, 2857, 2865 |
Total Applications | 2284 |
Issued Applications | 2045 |
Pending Applications | 88 |
Abandoned Applications | 151 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 8904242
[patent_doc_number] => 20130171744
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-04
[patent_title] => 'METHODS OF THERMALLY TREATING A SEMICONDUCTOR WAFER'
[patent_app_type] => utility
[patent_app_number] => 13/715099
[patent_app_country] => US
[patent_app_date] => 2012-12-14
[patent_effective_date] => 0000-00-00
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Array
(
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[patent_doc_number] => 20140167227
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[patent_kind] => A1
[patent_issue_date] => 2014-06-19
[patent_title] => 'METHOD OF MAKING A SEMICONDUCTOR DEVICE USING MULTIPLE LAYER SETS'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/714756 | Method of making a semiconductor device using multiple layer sets | Dec 13, 2012 | Issued |
Array
(
[id] => 9546153
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[patent_kind] => A1
[patent_issue_date] => 2014-06-19
[patent_title] => 'METHODS OF FABRICATING A PHOTOVOLTAIC MODULE, AND RELATED SYSTEM'
[patent_app_type] => utility
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Array
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[patent_issue_date] => 2013-06-13
[patent_title] => 'SEMICONDUCTOR MODULES AND METHODS OF FORMING THE SAME'
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Array
(
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Array
(
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[patent_title] => 'Super junction semiconductor device comprising a cell area and an edge area'
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Array
(
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[patent_title] => 'SEMICONDUCTOR DEVICE WITH ENCAPSULANT'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/664418 | Semiconductor device with encapsulant | Oct 30, 2012 | Issued |
Array
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[id] => 9446273
[patent_doc_number] => 20140117441
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[patent_title] => 'POWER DEVICE STRUCTURES AND METHODS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/660622 | POWER DEVICE STRUCTURES AND METHODS | Oct 24, 2012 | Abandoned |
Array
(
[id] => 9418789
[patent_doc_number] => 20140103439
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[patent_issue_date] => 2014-04-17
[patent_title] => 'Transistor Device and Method for Producing a Transistor Device'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/651603 | Transistor Device and Method for Producing a Transistor Device | Oct 14, 2012 | Abandoned |
Array
(
[id] => 9394051
[patent_doc_number] => 20140091457
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-04-03
[patent_title] => 'CONTROLLED SOLDER HEIGHT PACKAGES AND ASSEMBLY PROCESSES'
[patent_app_type] => utility
[patent_app_number] => 13/631939
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/631939 | Controlled solder height packages and assembly processes | Sep 28, 2012 | Issued |
Array
(
[id] => 8916397
[patent_doc_number] => 20130178022
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-11
[patent_title] => 'METHOD FOR FABRICATING TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/618186 | METHOD FOR FABRICATING TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN | Sep 13, 2012 | Abandoned |
Array
(
[id] => 9086243
[patent_doc_number] => 08557670
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-10-15
[patent_title] => 'SOI lateral bipolar junction transistor having a wide band gap emitter contact'
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Array
(
[id] => 9020272
[patent_doc_number] => 08530257
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-09-10
[patent_title] => 'Band offset in alingap based light emitters to improve temperature performance'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/595837 | Band offset in alingap based light emitters to improve temperature performance | Aug 26, 2012 | Issued |
Array
(
[id] => 9280900
[patent_doc_number] => 20140030868
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[patent_title] => 'DEPOSIT/ETCH FOR TAPERED OXIDE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/558218 | Deposit/etch for tapered oxide | Jul 24, 2012 | Issued |
Array
(
[id] => 8637631
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Array
(
[id] => 8617783
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/553392 | Method of manufacturing a pillar-type vertical transistor | Jul 18, 2012 | Issued |
Array
(
[id] => 8976775
[patent_doc_number] => 20130210205
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[patent_kind] => A1
[patent_issue_date] => 2013-08-15
[patent_title] => 'MANUFACTURING METHOD OF POWER TRANSISTOR DEVICE WITH SUPER JUNCTION'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/553806 | Manufacturing method of power transistor device with super junction | Jul 18, 2012 | Issued |
Array
(
[id] => 9220279
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[patent_title] => 'FIELD EFFECT TRANSISTOR DEVICES HAVING THICK GATE DIELECTRIC LAYERS AND THIN GATE DIELECTRIC LAYERS'
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Array
(
[id] => 8617767
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[patent_title] => 'FABRICATION OF LIGHT EMITTING DIODES (LEDS) USING A DEGAS PROCESS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/552344 | FABRICATION OF LIGHT EMITTING DIODES (LEDS) USING A DEGAS PROCESS | Jul 17, 2012 | Abandoned |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/552035 | Method of simultaneously forming multiple structures having different critical dimensions using sidewall transfer | Jul 17, 2012 | Issued |