Bryan Bui

Array ( [id] => 10022275 [patent_doc_number] => 09064770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-23 [patent_title] => 'Methods for minimizing edge peeling in the manufacturing of BSI chips' [patent_app_type] => utility [patent_app_number] => 13/551457 [patent_app_country] => US [patent_app_date] => 2012-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3066 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13551457 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9059768 [patent_doc_number] => 08546203 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-01 [patent_title] => 'Semiconductor structure having NFET extension last implants' [patent_app_type] => utility [patent_app_number] => 13/551100 [patent_app_country] => US [patent_app_date] => 2012-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 4245 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13551100 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9269264 [patent_doc_number] => 20140024181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-23 [patent_title] => 'SEMICONDUCTOR STRUCTURE HAVING NFET EXTENSION LAST IMPLANTS' [patent_app_type] => utility [patent_app_number] => 13/551054 [patent_app_country] => US [patent_app_date] => 2012-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 3500 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13551054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8612350 [patent_doc_number] => 20130017662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-17 [patent_title] => 'FILLER FOR FILLING A GAP, METHOD OF PREPARING THE SAME AND METHOD OF MANUFACTURING SEMICONDUCTOR CAPACITOR USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/548519 [patent_app_country] => US [patent_app_date] => 2012-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6339 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13548519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9223077 [patent_doc_number] => 20140017852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'METHODS FOR FLIP CHIP STACKING' [patent_app_type] => utility [patent_app_number] => 13/548029 [patent_app_country] => US [patent_app_date] => 2012-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6706 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13548029 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8932529 [patent_doc_number] => 08492228 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-23 [patent_title] => 'Field effect transistor devices having thick gate dielectric layers and thin gate dielectric layers' [patent_app_type] => utility [patent_app_number] => 13/547647 [patent_app_country] => US [patent_app_date] => 2012-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 4091 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13547647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8744939 [patent_doc_number] => 20130084656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/548088 [patent_app_country] => US [patent_app_date] => 2012-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6487 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13548088 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8612328 [patent_doc_number] => 20130017640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-17 [patent_title] => 'METHOD OF PROCESSING OPTICAL DEVICE WAFER' [patent_app_type] => utility [patent_app_number] => 13/546219 [patent_app_country] => US [patent_app_date] => 2012-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4367 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13546219 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8612327 [patent_doc_number] => 20130017639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-17 [patent_title] => 'METHOD FOR PRODUCING A GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/545902 [patent_app_country] => US [patent_app_date] => 2012-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4213 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13545902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9212165 [patent_doc_number] => 20140011342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'METHODS AND APPARATUSES FOR FORMING SEMICONDUCTOR FILMS' [patent_app_type] => utility [patent_app_number] => 13/544562 [patent_app_country] => US [patent_app_date] => 2012-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 14641 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13544562 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9107699 [patent_doc_number] => 20130280831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'PERMANENTLY BONDED FLUID CHANNEL NOZZLE PLATE FABRICATION' [patent_app_type] => utility [patent_app_number] => 13/454410 [patent_app_country] => US [patent_app_date] => 2012-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7207 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13454410 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9099462 [patent_doc_number] => 08563335 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-22 [patent_title] => 'Method of controlling polishing using in-situ optical monitoring and fourier transform' [patent_app_type] => utility [patent_app_number] => 13/454002 [patent_app_country] => US [patent_app_date] => 2012-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 6147 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13454002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8880789 [patent_doc_number] => 20130153973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'IMAGE SENSOR PIXELS WITH JUNCTION GATE PHOTODIODES' [patent_app_type] => utility [patent_app_number] => 13/450154 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4015 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9951649 [patent_doc_number] => 09000440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-07 [patent_title] => 'Thin film transistor, method of manufacturing thin film transistor, and organic light emitting diode display' [patent_app_type] => utility [patent_app_number] => 13/449403 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3930 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13449403 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8474414 [patent_doc_number] => 20120273821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'METHOD FOR PATTERNING AN EPITAXIAL SUBSTRATE, A LIGHT EMITTING DIODE AND A METHOD FOR FORMING A LIGHT EMITTING DIODE' [patent_app_type] => utility [patent_app_number] => 13/450424 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4220 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450424 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10557108 [patent_doc_number] => 09281313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Single poly non-volatile memory cells' [patent_app_type] => utility [patent_app_number] => 13/449822 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4555 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13449822 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8335661 [patent_doc_number] => 20120202364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'COMPLIANT CONDUCTIVE NANO-PARTICLE ELECTRICAL INTERCONNECT' [patent_app_type] => utility [patent_app_number] => 13/448914 [patent_app_country] => US [patent_app_date] => 2012-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13448914 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9091295 [patent_doc_number] => 20130270606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'Semiconductor Device with Integrated Breakdown Protection' [patent_app_type] => utility [patent_app_number] => 13/448994 [patent_app_country] => US [patent_app_date] => 2012-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10530 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13448994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9663023 [patent_doc_number] => 08810007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Wiring board, semiconductor device, and method for manufacturing wiring board' [patent_app_type] => utility [patent_app_number] => 13/449034 [patent_app_country] => US [patent_app_date] => 2012-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 39 [patent_no_of_words] => 9106 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13449034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9091303 [patent_doc_number] => 20130270614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'FORMATION OF A TRENCH SILICIDE' [patent_app_type] => utility [patent_app_number] => 13/448513 [patent_app_country] => US [patent_app_date] => 2012-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9295 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 22 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13448513 [rel_patent_id] =>[rel_patent_doc_number] =>)