Search

Bryan J. Jaketic

Examiner (ID: 12300)

Most Active Art Unit
3652
Art Unit(s)
3652, 3617, 2167, 3627
Total Applications
255
Issued Applications
202
Pending Applications
28
Abandoned Applications
25

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3796853 [patent_doc_number] => 05819072 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Method of using a four-state simulator for testing integrated circuit designs having variable timing constraints' [patent_app_type] => 1 [patent_app_number] => 8/671432 [patent_app_country] => US [patent_app_date] => 1996-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5948 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/819/05819072.pdf [firstpage_image] =>[orig_patent_app_number] => 671432 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/671432
Method of using a four-state simulator for testing integrated circuit designs having variable timing constraints Jun 26, 1996 Issued
Array ( [id] => 3939500 [patent_doc_number] => 05877965 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Parallel hierarchical timing correction' [patent_app_type] => 1 [patent_app_number] => 8/671030 [patent_app_country] => US [patent_app_date] => 1996-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2349 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877965.pdf [firstpage_image] =>[orig_patent_app_number] => 671030 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/671030
Parallel hierarchical timing correction Jun 23, 1996 Issued
Array ( [id] => 3894745 [patent_doc_number] => 05799170 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Simplified buffer manipulation using standard repowering function' [patent_app_type] => 1 [patent_app_number] => 8/666696 [patent_app_country] => US [patent_app_date] => 1996-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3230 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/799/05799170.pdf [firstpage_image] =>[orig_patent_app_number] => 666696 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/666696
Simplified buffer manipulation using standard repowering function Jun 17, 1996 Issued
Array ( [id] => 3857592 [patent_doc_number] => 05848262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Simulating digital systems by using vector processing' [patent_app_type] => 1 [patent_app_number] => 8/664483 [patent_app_country] => US [patent_app_date] => 1996-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3542 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/848/05848262.pdf [firstpage_image] =>[orig_patent_app_number] => 664483 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/664483
Simulating digital systems by using vector processing Jun 16, 1996 Issued
Array ( [id] => 3849983 [patent_doc_number] => 05761488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Logic translation method for increasing simulation emulation efficiency' [patent_app_type] => 1 [patent_app_number] => 8/662383 [patent_app_country] => US [patent_app_date] => 1996-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8445 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761488.pdf [firstpage_image] =>[orig_patent_app_number] => 662383 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/662383
Logic translation method for increasing simulation emulation efficiency Jun 12, 1996 Issued
Array ( [id] => 3841757 [patent_doc_number] => 05784594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Generic interactive device model wrapper' [patent_app_type] => 1 [patent_app_number] => 8/664020 [patent_app_country] => US [patent_app_date] => 1996-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2398 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784594.pdf [firstpage_image] =>[orig_patent_app_number] => 664020 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/664020
Generic interactive device model wrapper Jun 11, 1996 Issued
Array ( [id] => 3904929 [patent_doc_number] => 05778212 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Interprocedural analysis user interface' [patent_app_type] => 1 [patent_app_number] => 8/657196 [patent_app_country] => US [patent_app_date] => 1996-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7330 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/778/05778212.pdf [firstpage_image] =>[orig_patent_app_number] => 657196 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/657196
Interprocedural analysis user interface Jun 2, 1996 Issued
Array ( [id] => 3796797 [patent_doc_number] => 05819068 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Temporally driven simulation engine' [patent_app_type] => 1 [patent_app_number] => 8/656795 [patent_app_country] => US [patent_app_date] => 1996-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 5441 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/819/05819068.pdf [firstpage_image] =>[orig_patent_app_number] => 656795 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/656795
Temporally driven simulation engine May 30, 1996 Issued
Array ( [id] => 3860854 [patent_doc_number] => 05745883 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Billing system for use with document processing system' [patent_app_type] => 1 [patent_app_number] => 8/657716 [patent_app_country] => US [patent_app_date] => 1996-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4945 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/745/05745883.pdf [firstpage_image] =>[orig_patent_app_number] => 657716 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/657716
Billing system for use with document processing system May 29, 1996 Issued
Array ( [id] => 3898296 [patent_doc_number] => 05894565 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Field programmable gate array with distributed RAM and increased cell utilization' [patent_app_type] => 1 [patent_app_number] => 8/650477 [patent_app_country] => US [patent_app_date] => 1996-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 11732 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894565.pdf [firstpage_image] =>[orig_patent_app_number] => 650477 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/650477
Field programmable gate array with distributed RAM and increased cell utilization May 19, 1996 Issued
Array ( [id] => 4060750 [patent_doc_number] => 05870310 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Method and apparatus for designing re-usable core interface shells' [patent_app_type] => 1 [patent_app_number] => 8/642393 [patent_app_country] => US [patent_app_date] => 1996-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5256 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870310.pdf [firstpage_image] =>[orig_patent_app_number] => 642393 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/642393
Method and apparatus for designing re-usable core interface shells May 2, 1996 Issued
Array ( [id] => 3794436 [patent_doc_number] => 05809286 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Method and apparatus for emulating a dynamically configured digital cross-connect switch network' [patent_app_type] => 1 [patent_app_number] => 8/641458 [patent_app_country] => US [patent_app_date] => 1996-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 13331 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809286.pdf [firstpage_image] =>[orig_patent_app_number] => 641458 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/641458
Method and apparatus for emulating a dynamically configured digital cross-connect switch network Apr 30, 1996 Issued
Array ( [id] => 4081569 [patent_doc_number] => 05867689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Method and apparatus for emulating a digital cross-connect switch network using a flexible topology to test MCS network management' [patent_app_type] => 1 [patent_app_number] => 8/641461 [patent_app_country] => US [patent_app_date] => 1996-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12338 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867689.pdf [firstpage_image] =>[orig_patent_app_number] => 641461 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/641461
Method and apparatus for emulating a digital cross-connect switch network using a flexible topology to test MCS network management Apr 30, 1996 Issued
Array ( [id] => 3849942 [patent_doc_number] => 05761486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Method and apparatus for simulating a computer network system through collected data from the network' [patent_app_type] => 1 [patent_app_number] => 8/638771 [patent_app_country] => US [patent_app_date] => 1996-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 8027 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 397 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761486.pdf [firstpage_image] =>[orig_patent_app_number] => 638771 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/638771
Method and apparatus for simulating a computer network system through collected data from the network Apr 28, 1996 Issued
08/635406 ELECTROMAGNETIC FIELD INTENSITY COMPUTING DEVICE Apr 25, 1996 Abandoned
Array ( [id] => 3997977 [patent_doc_number] => 05949983 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Method to back annotate programmable logic device design files based on timing information of a target technology' [patent_app_type] => 1 [patent_app_number] => 8/634478 [patent_app_country] => US [patent_app_date] => 1996-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6343 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949983.pdf [firstpage_image] =>[orig_patent_app_number] => 634478 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/634478
Method to back annotate programmable logic device design files based on timing information of a target technology Apr 17, 1996 Issued
Array ( [id] => 3894368 [patent_doc_number] => 05764961 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Predictable diverse data delivery enablement method and apparatus for ATM based computer system' [patent_app_type] => 1 [patent_app_number] => 8/624337 [patent_app_country] => US [patent_app_date] => 1996-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 9135 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764961.pdf [firstpage_image] =>[orig_patent_app_number] => 624337 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/624337
Predictable diverse data delivery enablement method and apparatus for ATM based computer system Apr 2, 1996 Issued
Array ( [id] => 3887808 [patent_doc_number] => 05838947 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Modeling, characterization and simulation of integrated circuit power behavior' [patent_app_type] => 1 [patent_app_number] => 8/633836 [patent_app_country] => US [patent_app_date] => 1996-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838947.pdf [firstpage_image] =>[orig_patent_app_number] => 633836 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/633836
Modeling, characterization and simulation of integrated circuit power behavior Apr 1, 1996 Issued
Array ( [id] => 3974564 [patent_doc_number] => 05937184 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Synthesis of application-specific subsystems by selective migration' [patent_app_type] => 1 [patent_app_number] => 8/627715 [patent_app_country] => US [patent_app_date] => 1996-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2387 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937184.pdf [firstpage_image] =>[orig_patent_app_number] => 627715 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/627715
Synthesis of application-specific subsystems by selective migration Mar 31, 1996 Issued
Array ( [id] => 3756375 [patent_doc_number] => 05801969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Method and apparatus for computational fluid dynamic analysis with error estimation functions' [patent_app_type] => 1 [patent_app_number] => 8/622002 [patent_app_country] => US [patent_app_date] => 1996-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 7872 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801969.pdf [firstpage_image] =>[orig_patent_app_number] => 622002 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/622002
Method and apparatus for computational fluid dynamic analysis with error estimation functions Mar 25, 1996 Issued
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