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Bryan P Bui

Examiner (ID: 16130)

Most Active Art Unit
2153
Art Unit(s)
2153
Total Applications
3
Issued Applications
0
Pending Applications
0
Abandoned Applications
3

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18295908 [patent_doc_number] => 20230105594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/074392 [patent_app_country] => US [patent_app_date] => 2022-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18074392 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/074392
Write circuit of memory device and method of operating the same Dec 1, 2022 Issued
Array ( [id] => 18283380 [patent_doc_number] => 20230098852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => VARIABLE VOLTAGE BIT LINE PRECHARGE [patent_app_type] => utility [patent_app_number] => 18/061320 [patent_app_country] => US [patent_app_date] => 2022-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18061320 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/061320
Variable voltage bit line precharge Dec 1, 2022 Issued
Array ( [id] => 18242946 [patent_doc_number] => 20230075257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => MULTILEVEL CONTENT ADDRESSABLE MEMORY, MULTILEVEL CODING METHOD OF AND MULTILEVEL SEARCHING METHOD [patent_app_type] => utility [patent_app_number] => 18/055855 [patent_app_country] => US [patent_app_date] => 2022-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18055855 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/055855
Multilevel content addressable memory, multilevel coding method of and multilevel searching method Nov 15, 2022 Issued
Array ( [id] => 18212036 [patent_doc_number] => 20230058300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => Identify the Programming Mode of Memory Cells based on Cell Statistics Obtained during Reading of the Memory Cells [patent_app_type] => utility [patent_app_number] => 17/980396 [patent_app_country] => US [patent_app_date] => 2022-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20725 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17980396 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/980396
Identify the Programming Mode of Memory Cells based on Cell Statistics Obtained during Reading of the Memory Cells Nov 2, 2022 Pending
Array ( [id] => 18164944 [patent_doc_number] => 20230031541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/967006 [patent_app_country] => US [patent_app_date] => 2022-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11957 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17967006 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/967006
Memory system performing read operation with read voltage Oct 16, 2022 Issued
Array ( [id] => 18322533 [patent_doc_number] => 20230120661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING [patent_app_type] => utility [patent_app_number] => 17/965684 [patent_app_country] => US [patent_app_date] => 2022-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13160 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17965684 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/965684
Semiconductor memory systems with on-die data buffering Oct 12, 2022 Issued
Array ( [id] => 18144662 [patent_doc_number] => 20230018514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SEMICONDUCTOR MEMORY SYSTEM INCLUDING FIRST AND SECOND SEMICONDUCTOR MEMORY CHIPS AND A COMMON SIGNAL LINE [patent_app_type] => utility [patent_app_number] => 17/956648 [patent_app_country] => US [patent_app_date] => 2022-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17956648 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/956648
Semiconductor memory system including first and second semiconductor memory chips and a common signal line Sep 28, 2022 Issued
Array ( [id] => 18285656 [patent_doc_number] => 20230101128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => DRAM INTERFACE MODE WITH IMPROVED CHANNEL INTEGRITY AND EFFICIENCY AT HIGH SIGNALING RATES [patent_app_type] => utility [patent_app_number] => 17/954086 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5683 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17954086 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/954086
Dram interface mode with improved channel integrity and efficiency at high signaling rates Sep 26, 2022 Issued
Array ( [id] => 19016044 [patent_doc_number] => 11922984 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Memory device having volatile and non-volatile memory cells [patent_app_type] => utility [patent_app_number] => 17/949305 [patent_app_country] => US [patent_app_date] => 2022-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9334 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17949305 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/949305
Memory device having volatile and non-volatile memory cells Sep 20, 2022 Issued
Array ( [id] => 18097030 [patent_doc_number] => 20220415371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => MEMORY SYSTEMS FOR HIGH SPEED SCHEDULING [patent_app_type] => utility [patent_app_number] => 17/902562 [patent_app_country] => US [patent_app_date] => 2022-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20207 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17902562 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/902562
Memory systems for high speed scheduling Sep 1, 2022 Issued
Array ( [id] => 18224970 [patent_doc_number] => 20230063964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => ELECTRONIC DEVICE, OVER-ERASE DETECTION AND ELIMINATION METHODS FOR MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/899167 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3012 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17899167 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/899167
Electronic device, over-erase detection and elimination methods for memory cells Aug 29, 2022 Issued
Array ( [id] => 18097034 [patent_doc_number] => 20220415375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/896956 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17896956 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/896956
Semiconductor device Aug 25, 2022 Issued
Array ( [id] => 18990831 [patent_doc_number] => 20240062800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => DYNAMIC RANDOM ACCESS MEMORY (DRAM) ROW HAMMERING MITIGATION [patent_app_type] => utility [patent_app_number] => 17/890022 [patent_app_country] => US [patent_app_date] => 2022-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17890022 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/890022
DYNAMIC RANDOM ACCESS MEMORY (DRAM) ROW HAMMERING MITIGATION Aug 16, 2022 Pending
Array ( [id] => 18585736 [patent_doc_number] => 20230268000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 17/888294 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17888294 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/888294
Memory array Aug 14, 2022 Issued
Array ( [id] => 18039725 [patent_doc_number] => 20220383942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => MEMORY AND OPERATION METHOD OF THE MEMORY [patent_app_type] => utility [patent_app_number] => 17/887554 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17887554 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/887554
Memory and operation method of the memory Aug 14, 2022 Issued
Array ( [id] => 18061431 [patent_doc_number] => 20220392517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => SEMICONDUCTOR DEVICE HAVING PDA FUNCTION [patent_app_type] => utility [patent_app_number] => 17/888083 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7754 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17888083 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/888083
Semiconductor device having PDA function Aug 14, 2022 Issued
Array ( [id] => 18008205 [patent_doc_number] => 20220366972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => SYSTEMS AND METHODS TO STORE MULTI-LEVEL DATA [patent_app_type] => utility [patent_app_number] => 17/876149 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876149 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876149
Systems and methods to store multi-level data Jul 27, 2022 Issued
Array ( [id] => 17992949 [patent_doc_number] => 20220358986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => SEMICONDUCTOR DEVICE VERIFYING SIGNAL SUPPLIED FROM OUTSIDE [patent_app_type] => utility [patent_app_number] => 17/872771 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12586 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872771 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/872771
Semiconductor device verifying signal supplied from outside Jul 24, 2022 Issued
Array ( [id] => 19016062 [patent_doc_number] => 11923002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Varying-polarity read operations for polarity-written memory cells [patent_app_type] => utility [patent_app_number] => 17/869649 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 16601 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869649 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869649
Varying-polarity read operations for polarity-written memory cells Jul 19, 2022 Issued
Array ( [id] => 18285838 [patent_doc_number] => 20230101310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => EARLY DETECTION OF COMPRESSION STATUS USING INLINE METADATA [patent_app_type] => utility [patent_app_number] => 17/865102 [patent_app_country] => US [patent_app_date] => 2022-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10006 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17865102 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/865102
EARLY DETECTION OF COMPRESSION STATUS USING INLINE METADATA Jul 13, 2022 Pending
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