![](/images/general/no_picture/200_user.png)
Bryan P Bui
Examiner (ID: 16130)
Most Active Art Unit | 2153 |
Art Unit(s) | 2153 |
Total Applications | 3 |
Issued Applications | 0 |
Pending Applications | 0 |
Abandoned Applications | 3 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 17630299
[patent_doc_number] => 20220165314
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-26
[patent_title] => OPERATING METHOD OF HOST DEVICE AND MEMORY DEVICE AND MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 17/400368
[patent_app_country] => US
[patent_app_date] => 2021-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9611
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17400368
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/400368 | Operating method of host device and memory device and memory system | Aug 11, 2021 | Issued |
Array
(
[id] => 18182713
[patent_doc_number] => 20230043443
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-09
[patent_title] => MIM EFUSE MEMORY DEVICES AND FABRICATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/396398
[patent_app_country] => US
[patent_app_date] => 2021-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7682
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396398
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/396398 | MIM efuse memory devices and fabrication method thereof | Aug 5, 2021 | Issued |
Array
(
[id] => 17992937
[patent_doc_number] => 20220358974
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-10
[patent_title] => PIPE LATCH CIRCUIT FOR EXECUTING CONSECUTIVE DATA OUTPUT OPERATION
[patent_app_type] => utility
[patent_app_number] => 17/395809
[patent_app_country] => US
[patent_app_date] => 2021-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7359
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395809
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/395809 | Pipe latch circuit for executing consecutive data output operation | Aug 5, 2021 | Issued |
Array
(
[id] => 18190427
[patent_doc_number] => 11581028
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-14
[patent_title] => Memory device for counting fail bits included in sensed data
[patent_app_type] => utility
[patent_app_number] => 17/395352
[patent_app_country] => US
[patent_app_date] => 2021-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 16
[patent_no_of_words] => 10380
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395352
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/395352 | Memory device for counting fail bits included in sensed data | Aug 4, 2021 | Issued |
Array
(
[id] => 18073500
[patent_doc_number] => 11532337
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-12-20
[patent_title] => Multilevel content addressable memory, multilevel coding method of and multilevel searching method
[patent_app_type] => utility
[patent_app_number] => 17/383562
[patent_app_country] => US
[patent_app_date] => 2021-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 3256
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17383562
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/383562 | Multilevel content addressable memory, multilevel coding method of and multilevel searching method | Jul 22, 2021 | Issued |
Array
(
[id] => 18150399
[patent_doc_number] => 20230024257
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-26
[patent_title] => MEMORY DEVICE AND GLITCH PREVENTION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/382307
[patent_app_country] => US
[patent_app_date] => 2021-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3197
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17382307
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/382307 | Memory device and glitch prevention method thereof | Jul 20, 2021 | Issued |
Array
(
[id] => 17217517
[patent_doc_number] => 20210350855
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-11
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/381248
[patent_app_country] => US
[patent_app_date] => 2021-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6188
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 474
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17381248
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/381248 | Information processing system | Jul 20, 2021 | Issued |
Array
(
[id] => 18304232
[patent_doc_number] => 11626144
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-04-11
[patent_title] => Integrated multilevel memory apparatus and method of operating same
[patent_app_type] => utility
[patent_app_number] => 17/371890
[patent_app_country] => US
[patent_app_date] => 2021-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6892
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17371890
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/371890 | Integrated multilevel memory apparatus and method of operating same | Jul 8, 2021 | Issued |
Array
(
[id] => 17810594
[patent_doc_number] => 20220262429
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-18
[patent_title] => MEMORY AND OPERATION METHOD OF THE MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/365416
[patent_app_country] => US
[patent_app_date] => 2021-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3729
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365416
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/365416 | Memory and operation method of the memory | Jun 30, 2021 | Issued |
Array
(
[id] => 17900473
[patent_doc_number] => 20220310135
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-29
[patent_title] => DATA OUTPUT BUFFER AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/361018
[patent_app_country] => US
[patent_app_date] => 2021-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6664
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361018
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/361018 | Data output buffer and semiconductor apparatus including the same | Jun 27, 2021 | Issued |
Array
(
[id] => 17173847
[patent_doc_number] => 20210327518
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-21
[patent_title] => NON-VOLATILE MEMORY WITH ERASE VERIFY SKIP
[patent_app_type] => utility
[patent_app_number] => 17/359208
[patent_app_country] => US
[patent_app_date] => 2021-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16596
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359208
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/359208 | Non-volatile memory with erase verify skip | Jun 24, 2021 | Issued |
Array
(
[id] => 18053879
[patent_doc_number] => 11527270
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-13
[patent_title] => Hybrid library latch array
[patent_app_type] => utility
[patent_app_number] => 17/359253
[patent_app_country] => US
[patent_app_date] => 2021-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 18
[patent_no_of_words] => 4348
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359253
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/359253 | Hybrid library latch array | Jun 24, 2021 | Issued |
Array
(
[id] => 17660451
[patent_doc_number] => 20220180916
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-09
[patent_title] => MEMORY DEVICE HAVING PLANES
[patent_app_type] => utility
[patent_app_number] => 17/349421
[patent_app_country] => US
[patent_app_date] => 2021-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10724
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17349421
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/349421 | Memory device having planes | Jun 15, 2021 | Issued |
Array
(
[id] => 18174976
[patent_doc_number] => 11574693
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-07
[patent_title] => Memory apparatus and method of operation using periodic normal erase dummy cycle to improve stripe erase endurance and data retention
[patent_app_type] => utility
[patent_app_number] => 17/347772
[patent_app_country] => US
[patent_app_date] => 2021-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 23
[patent_no_of_words] => 14877
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17347772
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/347772 | Memory apparatus and method of operation using periodic normal erase dummy cycle to improve stripe erase endurance and data retention | Jun 14, 2021 | Issued |
Array
(
[id] => 17130052
[patent_doc_number] => 20210304821
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-30
[patent_title] => NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION
[patent_app_type] => utility
[patent_app_number] => 17/344146
[patent_app_country] => US
[patent_app_date] => 2021-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5995
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17344146
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/344146 | Nonvolatile semiconductor memory device which performs improved erase operation | Jun 9, 2021 | Issued |
Array
(
[id] => 18137112
[patent_doc_number] => 11562800
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-24
[patent_title] => Systems and methods for counting program-erase cycles of a cell block in a memory system
[patent_app_type] => utility
[patent_app_number] => 17/343486
[patent_app_country] => US
[patent_app_date] => 2021-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 17
[patent_no_of_words] => 10466
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17343486
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/343486 | Systems and methods for counting program-erase cycles of a cell block in a memory system | Jun 8, 2021 | Issued |
Array
(
[id] => 18061414
[patent_doc_number] => 20220392500
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-08
[patent_title] => PERFORMING READ OPERATIONS ON GROUPED MEMORY CELLS
[patent_app_type] => utility
[patent_app_number] => 17/342171
[patent_app_country] => US
[patent_app_date] => 2021-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8383
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 260
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17342171
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/342171 | Performing read operations on grouped memory cells | Jun 7, 2021 | Issued |
Array
(
[id] => 18219322
[patent_doc_number] => 11594268
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-28
[patent_title] => Memory device deserializer circuit with a reduced form factor
[patent_app_type] => utility
[patent_app_number] => 17/340754
[patent_app_country] => US
[patent_app_date] => 2021-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 11272
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340754
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/340754 | Memory device deserializer circuit with a reduced form factor | Jun 6, 2021 | Issued |
Array
(
[id] => 17956154
[patent_doc_number] => 11482267
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-25
[patent_title] => Memory device
[patent_app_type] => utility
[patent_app_number] => 17/330828
[patent_app_country] => US
[patent_app_date] => 2021-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 9308
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17330828
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/330828 | Memory device | May 25, 2021 | Issued |
Array
(
[id] => 17683210
[patent_doc_number] => 11367470
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-06-21
[patent_title] => Memory controller
[patent_app_type] => utility
[patent_app_number] => 17/321523
[patent_app_country] => US
[patent_app_date] => 2021-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5355
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17321523
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/321523 | Memory controller | May 16, 2021 | Issued |