
Bryce M. Aisaka
Examiner (ID: 9411, Phone: (571)270-5808 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851 |
| Total Applications | 790 |
| Issued Applications | 657 |
| Pending Applications | 52 |
| Abandoned Applications | 92 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18847386
[patent_doc_number] => 20230409790
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-21
[patent_title] => MACHINE LEARNING TECHNIQUES FOR CIRCUIT DESIGN DEBUGGING
[patent_app_type] => utility
[patent_app_number] => 17/846181
[patent_app_country] => US
[patent_app_date] => 2022-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7126
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17846181
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/846181 | Machine learning techniques for circuit design debugging | Jun 21, 2022 | Issued |
Array
(
[id] => 20610246
[patent_doc_number] => 12585848
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-03-24
[patent_title] => Machine learning techniques for circuit design verification
[patent_app_type] => utility
[patent_app_number] => 17/845784
[patent_app_country] => US
[patent_app_date] => 2022-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 1315
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17845784
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/845784 | Machine learning techniques for circuit design verification | Jun 20, 2022 | Issued |
Array
(
[id] => 19228662
[patent_doc_number] => 12008299
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-11
[patent_title] => Buffer insertion method and device, storage medium, and electronic device
[patent_app_type] => utility
[patent_app_number] => 17/806975
[patent_app_country] => US
[patent_app_date] => 2022-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 10383
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806975
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/806975 | Buffer insertion method and device, storage medium, and electronic device | Jun 14, 2022 | Issued |
Array
(
[id] => 18832953
[patent_doc_number] => 20230401480
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-14
[patent_title] => HARDWARE ACCELERATION OF MACHINE LEARNING DESIGNS
[patent_app_type] => utility
[patent_app_number] => 17/806906
[patent_app_country] => US
[patent_app_date] => 2022-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11703
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806906
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/806906 | Hardware acceleration of machine learning designs | Jun 13, 2022 | Issued |
Array
(
[id] => 20403754
[patent_doc_number] => 12493730
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-09
[patent_title] => Timing-aware and simultaneous optimization of latch clustering and placement in an integrated circuit
[patent_app_type] => utility
[patent_app_number] => 17/805198
[patent_app_country] => US
[patent_app_date] => 2022-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2985
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805198
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/805198 | Timing-aware and simultaneous optimization of latch clustering and placement in an integrated circuit | Jun 1, 2022 | Issued |
Array
(
[id] => 19369772
[patent_doc_number] => 12061857
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-08-13
[patent_title] => Post-CTS insertion delay and skew target reformulation of clock tree
[patent_app_type] => utility
[patent_app_number] => 17/829099
[patent_app_country] => US
[patent_app_date] => 2022-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 11749
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17829099
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/829099 | Post-CTS insertion delay and skew target reformulation of clock tree | May 30, 2022 | Issued |
Array
(
[id] => 19942515
[patent_doc_number] => 12314647
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-27
[patent_title] => Designing photonic integrated circuits based on arrays of inverse-designed components
[patent_app_type] => utility
[patent_app_number] => 17/828864
[patent_app_country] => US
[patent_app_date] => 2022-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 9925
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17828864
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/828864 | Designing photonic integrated circuits based on arrays of inverse-designed components | May 30, 2022 | Issued |
Array
(
[id] => 19905718
[patent_doc_number] => 12282725
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-22
[patent_title] => Enhanced alignment for global placement in a circuit
[patent_app_type] => utility
[patent_app_number] => 17/804070
[patent_app_country] => US
[patent_app_date] => 2022-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 4611
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17804070
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/804070 | Enhanced alignment for global placement in a circuit | May 24, 2022 | Issued |
Array
(
[id] => 19313429
[patent_doc_number] => 12039244
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-16
[patent_title] => Hybrid node chiplet stacking design
[patent_app_type] => utility
[patent_app_number] => 17/752474
[patent_app_country] => US
[patent_app_date] => 2022-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 9415
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17752474
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/752474 | Hybrid node chiplet stacking design | May 23, 2022 | Issued |
Array
(
[id] => 17839815
[patent_doc_number] => 20220277120
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-01
[patent_title] => SYSTEMS AND METHODS FOR MACHINE LEARNING BASED FAST STATIC THERMAL SOLVER
[patent_app_type] => utility
[patent_app_number] => 17/664241
[patent_app_country] => US
[patent_app_date] => 2022-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10200
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17664241
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/664241 | Systems and methods for machine learning based fast static thermal solver | May 19, 2022 | Issued |
Array
(
[id] => 19340658
[patent_doc_number] => 12050849
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-30
[patent_title] => Livelock detection in a hardware design using formal evaluation logic
[patent_app_type] => utility
[patent_app_number] => 17/749054
[patent_app_country] => US
[patent_app_date] => 2022-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 14173
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749054
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/749054 | Livelock detection in a hardware design using formal evaluation logic | May 18, 2022 | Issued |
Array
(
[id] => 18889655
[patent_doc_number] => 11868425
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-09
[patent_title] => Dynamic outlier bias reduction system and method
[patent_app_type] => utility
[patent_app_number] => 17/745596
[patent_app_country] => US
[patent_app_date] => 2022-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 11757
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 348
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17745596
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/745596 | Dynamic outlier bias reduction system and method | May 15, 2022 | Issued |
Array
(
[id] => 18774911
[patent_doc_number] => 20230369743
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-16
[patent_title] => SYMMETRIC MULTI-IC MODULES USING HIERARCHICAL DIGITAL RECONFIGURATION OF INTEGRATED CIRCUIT CHIPS
[patent_app_type] => utility
[patent_app_number] => 17/741677
[patent_app_country] => US
[patent_app_date] => 2022-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5761
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741677
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/741677 | Symmetric multi-IC modules using hierarchical digital reconfiguration of integrated circuit chips | May 10, 2022 | Issued |
Array
(
[id] => 17834260
[patent_doc_number] => 20220271564
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-25
[patent_title] => ELECTRONIC DEVICE FOR WIRELESSLY CHARGING EXTERNAL ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/662996
[patent_app_country] => US
[patent_app_date] => 2022-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11712
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17662996
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/662996 | Electronic device for wirelessly charging external electronic device | May 10, 2022 | Issued |
Array
(
[id] => 17855925
[patent_doc_number] => 20220285968
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-08
[patent_title] => PORTABLE PROPANE-FUELED BATTERY CHARGER
[patent_app_type] => utility
[patent_app_number] => 17/729397
[patent_app_country] => US
[patent_app_date] => 2022-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5262
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17729397
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/729397 | Portable propane-fueled battery charger | Apr 25, 2022 | Issued |
Array
(
[id] => 20329131
[patent_doc_number] => 12459394
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-04
[patent_title] => Electrical vehicle charging system for preventing of simultaneous closing of outlet contactors
[patent_app_type] => utility
[patent_app_number] => 17/725489
[patent_app_country] => US
[patent_app_date] => 2022-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 0
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 256
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17725489
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/725489 | Electrical vehicle charging system for preventing of simultaneous closing of outlet contactors | Apr 19, 2022 | Issued |
Array
(
[id] => 17763744
[patent_doc_number] => 20220237356
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-28
[patent_title] => Method And Structure For Mandrel And Spacer Patterning
[patent_app_type] => utility
[patent_app_number] => 17/720062
[patent_app_country] => US
[patent_app_date] => 2022-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8078
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17720062
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/720062 | Method and structure for mandrel and spacer patterning | Apr 12, 2022 | Issued |
Array
(
[id] => 20228680
[patent_doc_number] => 12417333
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-16
[patent_title] => Short net pin alignment for routing
[patent_app_type] => utility
[patent_app_number] => 17/656364
[patent_app_country] => US
[patent_app_date] => 2022-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4071
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17656364
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/656364 | Short net pin alignment for routing | Mar 23, 2022 | Issued |
Array
(
[id] => 19174137
[patent_doc_number] => 20240160111
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => DIGITAL DIRECT RECORDING DEVICE COMPRISING REAL TIME ANALYSIS AND CORRECTION OF RECORDED ARTWORK BY DIVIDING THE ARTWORK INTO SUBMODULES
[patent_app_type] => utility
[patent_app_number] => 18/550183
[patent_app_country] => US
[patent_app_date] => 2022-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4099
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18550183
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/550183 | DIGITAL DIRECT RECORDING DEVICE COMPRISING REAL TIME ANALYSIS AND CORRECTION OF RECORDED ARTWORK BY DIVIDING THE ARTWORK INTO SUBMODULES | Mar 10, 2022 | Pending |
Array
(
[id] => 19159468
[patent_doc_number] => 20240152175
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-09
[patent_title] => MANAGING ENERGY IN COMPUTATION WITH REVERSIBLE CIRCUITS
[patent_app_type] => utility
[patent_app_number] => 18/282035
[patent_app_country] => US
[patent_app_date] => 2022-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 23272
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 34
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18282035
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/282035 | MANAGING ENERGY IN COMPUTATION WITH REVERSIBLE CIRCUITS | Mar 10, 2022 | Pending |