Search

Bryce P. Bonzo

Supervisory Patent Examiner (ID: 19547, Phone: (571)272-3655 , Office: P/2113 )

Most Active Art Unit
2113
Art Unit(s)
2114, 2785, 2184, 2113
Total Applications
943
Issued Applications
814
Pending Applications
35
Abandoned Applications
97

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5990760 [patent_doc_number] => 20110099430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'METHOD AND SYSTEM TO MONITOR A DIVERSE HETEROGENEOUS APPLICATION ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 12/986877 [patent_app_country] => US [patent_app_date] => 2011-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10966 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20110099430.pdf [firstpage_image] =>[orig_patent_app_number] => 12986877 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/986877
Method and system to monitor a diverse heterogeneous application environment Jan 6, 2011 Issued
Array ( [id] => 8985166 [patent_doc_number] => 08516296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Efficient architecture for interfacing redundant devices to a distributed control system' [patent_app_type] => utility [patent_app_number] => 12/983958 [patent_app_country] => US [patent_app_date] => 2011-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4345 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12983958 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/983958
Efficient architecture for interfacing redundant devices to a distributed control system Jan 3, 2011 Issued
Array ( [id] => 8868198 [patent_doc_number] => 20130151901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'High Volume Recording of Instrumentation Data Varying Instrumentation Volumes to Prevent Data Loss' [patent_app_type] => utility [patent_app_number] => 12/974619 [patent_app_country] => US [patent_app_date] => 2010-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5297 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12974619 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/974619
High volume recording of instrumentation data varying instrumentation volumes to prevent data loss Dec 20, 2010 Issued
Array ( [id] => 8242515 [patent_doc_number] => 20120151253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'SYSTEM AND METHOD FOR MAINTAINING A DATA REDUNDANCY SCHEME IN A SOLID STATE MEMORY IN THE EVENT OF A POWER LOSS' [patent_app_type] => utility [patent_app_number] => 12/967206 [patent_app_country] => US [patent_app_date] => 2010-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2306 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12967206 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/967206
System and method for maintaining a data redundancy scheme in a solid state memory in the event of a power loss Dec 13, 2010 Issued
Array ( [id] => 9235997 [patent_doc_number] => 08601313 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-12-03 [patent_title] => 'System and method for a data reliability scheme in a solid state memory' [patent_app_type] => utility [patent_app_number] => 12/966892 [patent_app_country] => US [patent_app_date] => 2010-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4160 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12966892 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/966892
System and method for a data reliability scheme in a solid state memory Dec 12, 2010 Issued
Array ( [id] => 8242542 [patent_doc_number] => 20120151276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'Early Detection of Failing Computers' [patent_app_type] => utility [patent_app_number] => 12/965934 [patent_app_country] => US [patent_app_date] => 2010-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5242 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12965934 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/965934
Early detection of failing computers Dec 12, 2010 Issued
Array ( [id] => 8242543 [patent_doc_number] => 20120151278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'ADVANCED MANAGEMENT OF RUNTIME ERRORS' [patent_app_type] => utility [patent_app_number] => 12/965973 [patent_app_country] => US [patent_app_date] => 2010-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12965973 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/965973
Advanced management of runtime errors Dec 12, 2010 Issued
Array ( [id] => 9555707 [patent_doc_number] => 08762779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'Multi-core processor with external instruction execution rate heartbeat' [patent_app_type] => utility [patent_app_number] => 12/964949 [patent_app_country] => US [patent_app_date] => 2010-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 9258 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12964949 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/964949
Multi-core processor with external instruction execution rate heartbeat Dec 9, 2010 Issued
Array ( [id] => 8775472 [patent_doc_number] => 08429448 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-23 [patent_title] => 'Systems and methods for dynamic transaction migration in an event-driven, multi-silo architecture' [patent_app_type] => utility [patent_app_number] => 12/965511 [patent_app_country] => US [patent_app_date] => 2010-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9299 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12965511 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/965511
Systems and methods for dynamic transaction migration in an event-driven, multi-silo architecture Dec 9, 2010 Issued
Array ( [id] => 8872996 [patent_doc_number] => 08468383 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-18 [patent_title] => 'Reduced power failover system' [patent_app_type] => utility [patent_app_number] => 12/963383 [patent_app_country] => US [patent_app_date] => 2010-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7277 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12963383 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/963383
Reduced power failover system Dec 7, 2010 Issued
Array ( [id] => 8230050 [patent_doc_number] => 20120144253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'HARD MEMORY ARRAY FAILURE RECOVERY UTILIZING LOCKING STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/961947 [patent_app_country] => US [patent_app_date] => 2010-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6838 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12961947 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/961947
Hard memory array failure recovery utilizing locking structure Dec 6, 2010 Issued
Array ( [id] => 8143553 [patent_doc_number] => 20120096321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'BLOCK MANAGEMENT METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/960546 [patent_app_country] => US [patent_app_date] => 2010-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9632 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20120096321.pdf [firstpage_image] =>[orig_patent_app_number] => 12960546 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/960546
Block management method, memory controller, and memory storage apparatus Dec 5, 2010 Issued
Array ( [id] => 8716198 [patent_doc_number] => 08402349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Two dimensional data randomization for a memory' [patent_app_type] => utility [patent_app_number] => 12/961272 [patent_app_country] => US [patent_app_date] => 2010-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 7589 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12961272 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/961272
Two dimensional data randomization for a memory Dec 5, 2010 Issued
Array ( [id] => 8861583 [patent_doc_number] => 08464137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-11 [patent_title] => 'Probabilistic multi-tier error correction in not-and (NAND) flash memory' [patent_app_type] => utility [patent_app_number] => 12/960004 [patent_app_country] => US [patent_app_date] => 2010-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7753 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12960004 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/960004
Probabilistic multi-tier error correction in not-and (NAND) flash memory Dec 2, 2010 Issued
Array ( [id] => 9062931 [patent_doc_number] => 08549385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-01 [patent_title] => 'Soft decoding for quantizied channel' [patent_app_type] => utility [patent_app_number] => 12/959891 [patent_app_country] => US [patent_app_date] => 2010-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4989 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12959891 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/959891
Soft decoding for quantizied channel Dec 2, 2010 Issued
Array ( [id] => 8716191 [patent_doc_number] => 08402343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Reliable packet cut-through' [patent_app_type] => utility [patent_app_number] => 12/958745 [patent_app_country] => US [patent_app_date] => 2010-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 7598 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12958745 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/958745
Reliable packet cut-through Dec 1, 2010 Issued
Array ( [id] => 8787126 [patent_doc_number] => 08433981 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-30 [patent_title] => 'Coding across data blocks to reduce write amplification in NAND flash' [patent_app_type] => utility [patent_app_number] => 12/959101 [patent_app_country] => US [patent_app_date] => 2010-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3579 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12959101 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/959101
Coding across data blocks to reduce write amplification in NAND flash Dec 1, 2010 Issued
Array ( [id] => 7542942 [patent_doc_number] => 08060791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-15 [patent_title] => 'Annotating GUI test automation playback and debugging' [patent_app_type] => utility [patent_app_number] => 12/906842 [patent_app_country] => US [patent_app_date] => 2010-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4812 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/060/08060791.pdf [firstpage_image] =>[orig_patent_app_number] => 12906842 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/906842
Annotating GUI test automation playback and debugging Oct 17, 2010 Issued
Array ( [id] => 9062896 [patent_doc_number] => 08549350 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-01 [patent_title] => 'Multi-tier recovery' [patent_app_type] => utility [patent_app_number] => 12/895840 [patent_app_country] => US [patent_app_date] => 2010-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3704 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12895840 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/895840
Multi-tier recovery Sep 29, 2010 Issued
Array ( [id] => 8716167 [patent_doc_number] => 08402319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Method and system to extract a navigation model for analysis of a web application' [patent_app_type] => utility [patent_app_number] => 12/895323 [patent_app_country] => US [patent_app_date] => 2010-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6115 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12895323 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/895323
Method and system to extract a navigation model for analysis of a web application Sep 29, 2010 Issued
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