Search

Bryon P Gehman

Examiner (ID: 6873, Phone: (571)272-4555 , Office: P/3728 )

Most Active Art Unit
3736
Art Unit(s)
2401, 1615, 3629, 2899, 3501, 2404, 3728, 3203, 3208, 3736
Total Applications
4811
Issued Applications
3504
Pending Applications
257
Abandoned Applications
1095

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17106343 [patent_doc_number] => 11126560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => System-on-chip module for avoiding redundant memory access [patent_app_type] => utility [patent_app_number] => 16/867758 [patent_app_country] => US [patent_app_date] => 2020-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3361 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16867758 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/867758
System-on-chip module for avoiding redundant memory access May 5, 2020 Issued
Array ( [id] => 16772613 [patent_doc_number] => 10983717 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-20 [patent_title] => Uninterrupted block-based restore using a conditional construction container [patent_app_type] => utility [patent_app_number] => 15/929438 [patent_app_country] => US [patent_app_date] => 2020-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6999 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15929438 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/929438
Uninterrupted block-based restore using a conditional construction container Apr 30, 2020 Issued
Array ( [id] => 16788093 [patent_doc_number] => 10990526 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-27 [patent_title] => Handling asynchronous power loss in a memory sub-system that programs sequentially [patent_app_type] => utility [patent_app_number] => 15/929405 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15929405 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/929405
Handling asynchronous power loss in a memory sub-system that programs sequentially Apr 29, 2020 Issued
Array ( [id] => 16818750 [patent_doc_number] => 11003580 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-11 [patent_title] => Managing overlapping reads and writes in a data cache [patent_app_type] => utility [patent_app_number] => 15/929407 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 7136 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15929407 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/929407
Managing overlapping reads and writes in a data cache Apr 29, 2020 Issued
Array ( [id] => 16818771 [patent_doc_number] => 11003601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Memory system design using buffer(s) on a mother board [patent_app_type] => utility [patent_app_number] => 16/837844 [patent_app_country] => US [patent_app_date] => 2020-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16837844 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/837844
Memory system design using buffer(s) on a mother board Mar 31, 2020 Issued
Array ( [id] => 16160691 [patent_doc_number] => 20200218578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => Communication Fabric Coupled Compute Units [patent_app_type] => utility [patent_app_number] => 16/819646 [patent_app_country] => US [patent_app_date] => 2020-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13664 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16819646 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/819646
Communication fabric coupled compute units Mar 15, 2020 Issued
Array ( [id] => 17031333 [patent_doc_number] => 11093144 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-17 [patent_title] => Non-disruptive transformation of a logical storage device from a first access protocol to a second access protocol [patent_app_type] => utility [patent_app_number] => 16/793262 [patent_app_country] => US [patent_app_date] => 2020-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 15285 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793262 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/793262
Non-disruptive transformation of a logical storage device from a first access protocol to a second access protocol Feb 17, 2020 Issued
Array ( [id] => 16018045 [patent_doc_number] => 20200183866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => Communications Interface Between Host System and State Machine [patent_app_type] => utility [patent_app_number] => 16/788933 [patent_app_country] => US [patent_app_date] => 2020-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16788933 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/788933
Communications interface between host system and state machine Feb 11, 2020 Issued
Array ( [id] => 15998085 [patent_doc_number] => 20200174913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => ORTHOGONAL EXPERIMENTATION IN A COMPUTING ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 16/784648 [patent_app_country] => US [patent_app_date] => 2020-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7823 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16784648 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/784648
Orthogonal experimentation in a computing environment Feb 6, 2020 Issued
Array ( [id] => 16794672 [patent_doc_number] => 20210124489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => METHOD AND DEVICE FOR ADAPTIVELY IDENTIFYING TYPE OF FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 16/782113 [patent_app_country] => US [patent_app_date] => 2020-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16782113 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/782113
Method and device for adaptively identifying type of flash memory Feb 4, 2020 Issued
Array ( [id] => 16116665 [patent_doc_number] => 20200210355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => ACCELERATED DATA HANDLING IN CLOUD DATA STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 16/780009 [patent_app_country] => US [patent_app_date] => 2020-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16780009 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/780009
Accelerated data handling in cloud data storage system Feb 2, 2020 Issued
Array ( [id] => 15965643 [patent_doc_number] => 20200166573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => FALLING CLOCK EDGE JTAG BUS ROUTERS [patent_app_type] => utility [patent_app_number] => 16/776667 [patent_app_country] => US [patent_app_date] => 2020-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13538 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16776667 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/776667
First, second, and third bus leads, routing and control circuitry Jan 29, 2020 Issued
Array ( [id] => 16879721 [patent_doc_number] => 11029868 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-08 [patent_title] => Initialization code/data memory mapping system [patent_app_type] => utility [patent_app_number] => 16/775386 [patent_app_country] => US [patent_app_date] => 2020-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5773 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16775386 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/775386
Initialization code/data memory mapping system Jan 28, 2020 Issued
Array ( [id] => 16745008 [patent_doc_number] => 10969996 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-06 [patent_title] => Extendable hardware queue structure and method of operation thereof [patent_app_type] => utility [patent_app_number] => 15/929206 [patent_app_country] => US [patent_app_date] => 2020-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8224 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15929206 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/929206
Extendable hardware queue structure and method of operation thereof Jan 22, 2020 Issued
Array ( [id] => 16979722 [patent_doc_number] => 20210223959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => TRANSITIONING FROM AN ORIGINAL DEVICE TO A NEW DEVICE WITHIN A DATA STORAGE ARRAY [patent_app_type] => utility [patent_app_number] => 16/747811 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747811 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747811
Transitioning from an original device to a new device within a data storage array Jan 20, 2020 Issued
Array ( [id] => 15903231 [patent_doc_number] => 20200151135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => DATA TRANSMISSION CIRCUIT, AND SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE DATA TRANSMISSION CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/746339 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8454 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746339 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/746339
Data transmission circuit for operating a data bus inversion, and a semiconductor apparatus and a semiconductor system including the same Jan 16, 2020 Issued
Array ( [id] => 17091763 [patent_doc_number] => 11119953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Data access method and apparatus for accessing shared cache in a memory access manner [patent_app_type] => utility [patent_app_number] => 16/743139 [patent_app_country] => US [patent_app_date] => 2020-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 8468 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16743139 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/743139
Data access method and apparatus for accessing shared cache in a memory access manner Jan 14, 2020 Issued
Array ( [id] => 17106136 [patent_doc_number] => 11126351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Policy-based management of disk storage for consumer storge buckets [patent_app_type] => utility [patent_app_number] => 16/738923 [patent_app_country] => US [patent_app_date] => 2020-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8752 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16738923 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/738923
Policy-based management of disk storage for consumer storge buckets Jan 8, 2020 Issued
Array ( [id] => 16964714 [patent_doc_number] => 20210216213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => OPTIMIZING WRITE IO BANDWIDTH AND LATENCY IN AN ACTIVE-ACTIVE CLUSTERED SYSTEM USING STORAGE OBJECT AFFINITY TO A SINGLE STORAGE NODE [patent_app_type] => utility [patent_app_number] => 16/738405 [patent_app_country] => US [patent_app_date] => 2020-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9266 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16738405 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/738405
Optimizing write IO bandwidth and latency in an active-active clustered system based on a single storage node having ownership of a storage object Jan 8, 2020 Issued
Array ( [id] => 16950112 [patent_doc_number] => 20210208804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => MULTIPATH DEVICE PSEUDO NAME TO LOGICAL VOLUME MAPPING FOR HOST DEVICES [patent_app_type] => utility [patent_app_number] => 16/734526 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16734526 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/734526
Multipath device pseudo name to logical volume mapping for host devices Jan 5, 2020 Issued
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