Search

Bryon P Gehman

Examiner (ID: 6873, Phone: (571)272-4555 , Office: P/3728 )

Most Active Art Unit
3736
Art Unit(s)
2401, 1615, 3629, 2899, 3501, 2404, 3728, 3203, 3208, 3736
Total Applications
4811
Issued Applications
3504
Pending Applications
257
Abandoned Applications
1095

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17136499 [patent_doc_number] => 11138052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-05 [patent_title] => System and method for supporting data communication in a movable platform [patent_app_type] => utility [patent_app_number] => 16/729978 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10726 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16729978 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/729978
System and method for supporting data communication in a movable platform Dec 29, 2019 Issued
Array ( [id] => 16116663 [patent_doc_number] => 20200210354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => Integrated circuit I/O integrity and degradation monitoring [patent_app_type] => utility [patent_app_number] => 16/729680 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16729680 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/729680
Integrated circuit I/O integrity and degradation monitoring Dec 29, 2019 Issued
Array ( [id] => 15715011 [patent_doc_number] => 20200104272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => LOW POWER MULTILEVEL DRIVER FOR GENERATING WIRE SIGNALS ACCORDING TO SUMMATIONS OF A PLURALITY OF WEIGHTED ANALOG SIGNAL COMPONENTS HAVING WIRE-SPECIFIC SUB-CHANNEL WEIGHTS [patent_app_type] => utility [patent_app_number] => 16/702284 [patent_app_country] => US [patent_app_date] => 2019-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16702284 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/702284
Low power multilevel driver for generating wire signals according to summations of a plurality of weighted analog signal components having wire-specific sub-channel weights Dec 2, 2019 Issued
Array ( [id] => 15719741 [patent_doc_number] => 20200106638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => MEANS AND METHODS FOR REGULATING CAN COMMUNICATION [patent_app_type] => utility [patent_app_number] => 16/697723 [patent_app_country] => US [patent_app_date] => 2019-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16697723 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/697723
Means and methods for regulating CAN communication Nov 26, 2019 Issued
Array ( [id] => 16794684 [patent_doc_number] => 20210124501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => WRITE OPERATIONS TO MEMORY [patent_app_type] => utility [patent_app_number] => 16/665432 [patent_app_country] => US [patent_app_date] => 2019-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5806 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16665432 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/665432
Utilizing a link interface for performing partial write operations to memory Oct 27, 2019 Issued
Array ( [id] => 15772755 [patent_doc_number] => 20200117395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS [patent_app_type] => utility [patent_app_number] => 16/601913 [patent_app_country] => US [patent_app_date] => 2019-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9517 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16601913 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/601913
Multi-processor bridge with cache allocate awareness Oct 14, 2019 Issued
Array ( [id] => 17001390 [patent_doc_number] => 11080200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Allocation of machine learning tasks into a shared cache [patent_app_type] => utility [patent_app_number] => 16/601501 [patent_app_country] => US [patent_app_date] => 2019-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8325 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16601501 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/601501
Allocation of machine learning tasks into a shared cache Oct 13, 2019 Issued
Array ( [id] => 16299796 [patent_doc_number] => 20200285519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => CONTROLLER, MEMORY SYSTEM INCLUDING THE CONTROLLER, AND METHOD OF OPERATING THE MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/598560 [patent_app_country] => US [patent_app_date] => 2019-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16598560 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/598560
Controller, memory system including the controller, and memory allocation method of the memory system Oct 9, 2019 Issued
Array ( [id] => 16219440 [patent_doc_number] => 10735270 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-04 [patent_title] => Computer-based systems configured for network modelling and monitoring using programming object bindings and methods of use thereof [patent_app_type] => utility [patent_app_number] => 16/588685 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 23656 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 443 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16588685 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/588685
Computer-based systems configured for network modelling and monitoring using programming object bindings and methods of use thereof Sep 29, 2019 Issued
Array ( [id] => 16592666 [patent_doc_number] => 10901929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Input/output port rotation in a storage area network device [patent_app_type] => utility [patent_app_number] => 16/556177 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 10341 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16556177 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/556177
Input/output port rotation in a storage area network device Aug 28, 2019 Issued
Array ( [id] => 16636977 [patent_doc_number] => 10915487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Switching reduction bus using data bit inversion [patent_app_type] => utility [patent_app_number] => 16/553552 [patent_app_country] => US [patent_app_date] => 2019-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 9514 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16553552 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/553552
Switching reduction bus using data bit inversion Aug 27, 2019 Issued
Array ( [id] => 15561715 [patent_doc_number] => 20200065269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => NVMeoF Messages Between a Host and a Target [patent_app_type] => utility [patent_app_number] => 16/549476 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16549476 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/549476
Non-volatile memory express over fabric messages between a host and a target using a burst mode Aug 22, 2019 Issued
Array ( [id] => 15561709 [patent_doc_number] => 20200065266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => MEMORY BUS MR REGISTER PROGRAMMING PROCESS [patent_app_type] => utility [patent_app_number] => 16/529700 [patent_app_country] => US [patent_app_date] => 2019-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5814 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16529700 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/529700
Memory bus MR register programming process Jul 31, 2019 Issued
Array ( [id] => 15152105 [patent_doc_number] => 20190354530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => DEVICES, SYSTEMS, AND METHODS TO SYNCHRONIZE SIMULTANEOUS DMA PARALLEL PROCESSING OF A SINGLE DATA STREAM BY MULTIPLE DEVICES [patent_app_type] => utility [patent_app_number] => 16/527217 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16527217 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/527217
Devices, systems, and methods to synchronize simultaneous DMA parallel processing of a single data stream by multiple devices Jul 30, 2019 Issued
Array ( [id] => 16600023 [patent_doc_number] => 20210026554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => METHODS AND APPARATUS FOR SERVICING DATA ACCESS REQUESTS [patent_app_type] => utility [patent_app_number] => 16/521723 [patent_app_country] => US [patent_app_date] => 2019-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16521723 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/521723
Methods and apparatus for reconfiguring nodes and reissuing data access requests Jul 24, 2019 Issued
Array ( [id] => 16600015 [patent_doc_number] => 20210026546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => ENHANCED QUALITY OF SERVICE (QOS) FOR MULTIPLE SIMULTANEOUS REPLICATION SESSIONS IN A REPLICATION SETUP [patent_app_type] => utility [patent_app_number] => 16/521730 [patent_app_country] => US [patent_app_date] => 2019-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5173 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16521730 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/521730
Enhanced quality of service (QoS) for multiple simultaneous replication sessions in a replication setup Jul 24, 2019 Issued
Array ( [id] => 15440205 [patent_doc_number] => 20200034286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => USING HYBRID-SOFTWARE/HARDWARE BASED LOGICAL-TO-PHYSICAL ADDRESS MAPPING TO IMPROVE THE DATA WRITE THROUGHPUT OF SOLID-STATE DATA STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 16/521711 [patent_app_country] => US [patent_app_date] => 2019-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3528 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16521711 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/521711
Using hybrid-software/hardware based logical-to-physical address mapping to improve the data write throughput of solid-state data storage devices Jul 24, 2019 Issued
Array ( [id] => 16446977 [patent_doc_number] => 10838906 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-17 [patent_title] => Communication between transceiver and microcontroller [patent_app_type] => utility [patent_app_number] => 16/509304 [patent_app_country] => US [patent_app_date] => 2019-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16509304 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/509304
Communication between transceiver and microcontroller Jul 10, 2019 Issued
Array ( [id] => 16577224 [patent_doc_number] => 20210011625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => SYSTEM AND METHOD FOR BACKUP OF LOGICAL LAYER VIRTUAL SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/504847 [patent_app_country] => US [patent_app_date] => 2019-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16504847 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/504847
System and method for backup of virtual machines organized using logical layers Jul 7, 2019 Issued
Array ( [id] => 16577225 [patent_doc_number] => 20210011626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => MIRRORING WRITE OPERATIONS ACROSS DATA STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 16/505453 [patent_app_country] => US [patent_app_date] => 2019-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16505453 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/505453
Mirroring write operations across data storage devices Jul 7, 2019 Issued
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